Claims
- 1. A bidirectional repeater circuit, comprising:a first tristate driver comprising an output connected to a first bus for outputting a signal to the first bus; and a second tristate driver comprising an output connected to a second bus for outputting a signal to the second bus, wherein an input of the first tristate driver is connected to the second bus and an input of the second tristate driver bus is connected to the first bus, and wherein the first and second tristate drivers are alternatively enabled within a single clock cycle to transmit signals between the first and second bus in opposite directions during the single clock cycle.
- 2. The bidirectional repeater circuit of claim 1, wherein the first and second bus comprise a tristate bus.
- 3. The bidirectional repeater circuit of claim 1, further comprising a control circuit for generating a control signal to alternatively enable the first and second tristate drivers.
- 4. A bidirectional repeater circuit, comprising:a first tristate driver comprising an output connected to a first bus for outputting a signal to the first bus; a second tristate driver comprising an output connected to a second bus for outputting a signal to the second bus, wherein an input of the first tristate driver is connected to the second bus and an input of the second tristate driver bus is connected to the first bus, and wherein the first and second tristate drivers are alternatively enabled to transmit signals between the first and second bus; and a control circuit for generating a control signal to alternatively enable the first and second tristate drivers, wherein the control circuit generates the control signal from a timing signal that coordinates tristate bus operation.
- 5. A bidirectional repeater circuit, comprising:a first tristate driver comprising an output connected to a first bus for outputting a signal to the first bus; a second tristate driver comprising an output connected to a second bus for outputting a signal to the second bus, wherein an input of the first tristate driver is connected to the second bus and an input of the second tristate driver bus is connected to the first bus, and wherein the first and second tristate drivers are alternatively enabled to transmit signals between the first and second bus; and a control circuit for generating a control signal to alternatively enable the first and second tristate drivers, wherein the control circuit comprises a timing circuit that coordinates data transfer by the bidirectional repeater circuit between an entity and a swapper circuit.
- 6. The bidirectional repeater circuit of claim 1, wherein the first and second tristate drivers are enabled by a first control signal and a second control signal, respectively.
CROSS REFERENCE TO RELATED APPLICATION
This application is a Divisional of copending U.S. application Ser. No. 08/975,368, filed Nov. 22, 1997.
US Referenced Citations (17)
Foreign Referenced Citations (2)
Number |
Date |
Country |
57072435 |
May 1982 |
JP |
57083937 |
May 1982 |
JP |