Patent Application
20060215296
This disclosure generally relates to bidirectional communication links. In particular, this disclosure is directed to referenceless generation of a centering reference for a receive link circuit, such as a receive clock and data recovery circuit.
A bidirectional communication circuit may be configured to transmit data over a first data channel and receive data over a second data channel. The first and second data channels may collectively form a bidirectional channel, such as a SONET channel, a fiber optic channel, or any other bi-directional communication channel. The data may be transmitted and received over the first and second channels by a transmit clock and data recovery (CDR) circuit and a receive CDR, respectively. The transmit CDR and receive CDR may be configured to utilize a reference clock to obtain a correct locking frequency. The reference clock is used to provide approximate frequency information to a voltage controlled oscillator (VCO) within the CDR circuit. The frequency information is typically used to facilitate lock during an initial start up or under very jittery conditions. Once the locking frequency is obtained, a phase detector within the CDR circuit establishes and maintains a phase locked condition.
Disclosed herein is a bidirectional referenceless communication circuit that has the ability to provide approximate frequency information to the VCO within the receive CDR circuit without utilizing a reference clock. This capability results in a more robust bidirectional communication link, as the receive CDR circuit may obtain and maintain lock without a reference clock or upon failure of the reference clock. The bidirectional referenceless communication circuit includes a referenceless clocking generator circuit operable to receive a first clock signal recovered by a transmit CDR circuit and a second clock signal recovered by a received CDR circuit and compare the frequency of the second clock signal to the first clock signal to generate a referenceless clocking signal based on the comparison.
Similarly, the receive CDR 104 receives receive data (RX DATA) over a receive channel, recovers the clock, and relocks the received data. Clock recovery of the receive data is facilitated by the reference clock 106.
Matching the frequency of a serial data stream is insufficient to accurately recover the received data because the precise phase of the data stream must be taken into account as well. To properly recover the received clock and data, the incoming data stream 138 is compared to the clock signal 114 in a phase detector circuit 140. If a given transition or edge of the clock signal 114 lags or leads a corresponding edge of the receive data stream 138, then the detector circuit 140 outputs an UP or DOWN signal, respectively. This control signal is provided through a multiplexer 126 to the charge pump 130 to affect a slight upward or downward adjustment of the tune voltage VTune 136. This adjustment slightly increases or decreases the frequency of the clock signal 114 generated by the VCO 112 to synchronize the clock signal 114 with the received data stream 138.
The frequency detector 122 thus coarsely adjusts the VCO loop in order to drive the VCO 112 to an approximate desired frequency, and the phase detector 140 adjusts the phase of the clock signal 114 to synchronize it to the incoming data stream 138. When both loops are locked, the clock signal 114 provides the recovered clock signal and the recovered clock signal is used to clock the flip flop 150 to recover data from the incoming data stream.
The multiplexer 126 is arranged for controllably selecting the frequency detector 122 output or the phase detector 140 output as the control input to the charge pump 130 in response to a selection control signal 144. Generally, when the serial data stream 138 is being received, the clock signal 114 is at the correct frequency, i.e., the frequency of the serial data stream 138, and the multiplexer 126 selects the output of the phase detector 140 as a control input to the charge pump 130 to maintain synchronization between the recovered clock signal 114 and the data stream 138. If synchronization is lost, then the selection control signal 144 switches the multiplexer 126 to select the frequency detector 122 output as the control input to the charge pump 130 to force the VCO 112 to N times the reference clock signal 120 frequency.
Thus, the reference clock 120 is used to provide approximate frequency information to the VCO 112 when the correct locking frequency has not been established or is lost, such as may occur under noisy and/or jittery conditions. Typically the reference clock 120 primarily benefits the receive CDR circuit, as such noise and jitter is typically present in data received over a receive channel, but is not typically present in data that is to be transmitted over a transmission channel. Additionally, signal degradation in the transmit direction may be compensated for a priori (e.g., equalizing for a 30 millimeter electrical trace on a printed circuit board). Phase and frequency lock may thus often be obtained in the transmit CDR without a reference clock signal.
The referenceless clocking generator circuit 210 receives a first clock signal (TX CLOCK) recovered by the transmit CDR 202 and a second clock signal (RX CLOCK) recovered by the receive CDR 204 and provides a referenceless clocking signal 206 to the receive CDR 204. The referenceless clocking signal 206 is utilized to adjust a VCO within the receive CDR 204 to a desired clock frequency when the correct locking frequency has not been established or is lost, such as may occur under very noisy and/or jittery conditions.
The phase detector 230, charge pump and loop filter 238, VCO 240, and D-type flip flop 242 of the receive CDR 204 operate in a similar manner to the phase detector 220, charge pump and loop filter 222, VCO 224, and the D-type flip-flop 226 of the transmit CDR 202. When the receive CDR 204 is in a lock condition, the VCO 240 generates a second clock signal that is the recovered clock from the received data and reclocks the received data via the D-type flip-flop 242.
Because the receive data typically suffers from transmission degradation (e.g., noise and/or jitter), the receive CDR 204 may have difficulty in obtaining a lock condition. As described above, one method to facilitate phase and frequency lock is a reference signal. Accordingly, a referenceless clocking generator circuit may be provided that receives the first clock signal and the second clock signal and compares the frequency of the second clock signal to the first clock signal generates a referenceless clocking signal based on the comparison is provided. The referenceless clocking signal is utilized to facilitate phase and frequency lock in the receive CDR 204.
In the example of
A multiplexer 234 selects one of the phase detector 230 output signal or the frequency detector 232 output signal based on a selection signal provided by a lock detector circuit 236. The lock detector circuit 236 determines whether the frequency of the VCO 240 signal is within an acceptable range of the frequency of the VCO 224 signal, e.g., +/−100 ppm. If the frequency of the VCO 240 signal is within the acceptable range of the frequency of the VCO 224 signal, then the lock detector circuit 236 determines that the VCOs 240 and 224 are frequency locked and generates a selection signal that causes the multiplexor 234 to provide the phase detector output 230 to the charge pump and loop filter 238. Thereafter, the phase detector 230 determines if a given transition or edge of the VCO 240 signal lags or leads a corresponding edge of the received data and drives the charge pump and loop filter 238 in response to slightly increase or decrease the frequency of the VCO 240 signal to maintain lock.
If, however, the frequency of the VCO 240 signal is not within the acceptable range of the frequency of the VCO 224 signal, then the lock detector circuit 236 determines that the VCO 240 is not frequency locked to VCO 224. Based on this determination, the lock detector circuit 236 generates a selection signal that causes the multiplexor 234 to provide the frequency detector 232 output to the charge pump and loop filter 238. The referenceless clocking signal output by the frequency detector 232 then drives the charge pump and loop filter 238 accordingly to drive the frequency of the VCO 240 signal to the frequency of the VCO 224 signal. Once frequency lock is obtained, control of the VCO 240 is returned to the phase detector 230.
In another example circuit, the lock detector circuit 236 determines if the first clock signal and second clock signal are frequency locked by measuring the magnitude of the referenceless clocking signal output by the frequency detector 232. In this example circuit, the lock detector circuit 236 need only receive the output of the frequency detector circuit 232 to make this determination, and need not directly monitor the signals from VCO 224 and VCO 240.
The referenceless clocking generator of
While the example referenceless clocking generator of
In the example of
This written description sets forth the best mode of the claimed invention, and describes the claimed invention to enable a person of ordinary skill in the art to make and use it, by presenting examples of the elements recited in the claims. The patentable scope of the invention is defined by the claims themselves, and may include other examples that occur to those skilled in the art. Such other examples, which may be available either before or after the application filing date, are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.
