The present invention relates to bifurcate buffers and is particularly concerned with very high speed switch buffers.
Peripheral Component Interconnect Express, PCIe 2.0 specifies 5.0 Gigbit/s symbol rate per lane. Multiple lanes can be used to fabricate larger port bandwidths. For example, x4 port would have an aggregate symbol rate of 20 G, and a bit rate of 16 G, 8b10b coding is used. A x8 port would have an aggregate symbol rate of 40 G, and a bit rate of 32 G. There are other serial interconnect protocols, for example serial rapid IO and Ethernet that have similar properties. This disclosure will focus on PICe, but is not limited to that protocol.
Referring to
The numbers of bytes (actually a 10 bit symbol on the serial link) is shown in
The simplest way to convert this serial packet to a parallel bus for on chip processing is shown in
It is possible to have a serialize/de-serialize (SERDES) 30 that creates 16-bit wide data lanes running at half the speed. The issue then is that two packets may exist at the same time on the same clock tick. Memory management would required that different packets occupy different memory locations.
When a port bifurcates, prior art methods typically instantiate another buffer for that port. This buffer is wasted when a single 1×8 port is used.
An object of the present invention is to provide an improved bifurcate buffer.
In accordance with an aspect of the present invention there is provided a bifurcate buffer comprising a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, a plurality n of buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-nth that of the input data.
In accordance with another aspect of the present invention there is provided a A bifurcate buffer comprising a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, two buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers for buffering input data at a clock rate one-half that of the input data.
In accordance with a further aspect of the present invention there is provided a A bifurcate buffer comprising a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, two buffers and two media access controllers each having inputs coupled to one-half the plurality of de-serializers, data outputs coupled to the buffers, and a control output coupled to respective buffers for buffering input data at a clock rate one-half that of the input data.
By paralleling the data to wider widths and creating separate memories more effective use of buffers is made.
The present invention will be further understood from the following detailed description with reference to the drawings in which:
a and 5b illustrate packet flow for the bifurcate buffer of
a and 6b illustrate packet flow for the bifurcate buffer of
Referring to
In operation, the data is written into two-x64 250 MHz dual port RAM 44 and 46. The memory management generates different addresses for each bank.
Referring to
In operation, the upper x8 MAC 42 is configured to run in 4 mode. Here each buffer 44 and 54 is managed by its respective MAC 42 and 52.
Referring to
Referring to
Referring to
In 1×8 mode two packet pointers 82 and 84 index each packet. The 8-bit pointer also has another bit to indicate which pointer contains the first portion of the packet. This way packets can be pulled out of the buffer in order. The packet pointers are stored in a FIFO (in this example).
In 2×4 mode the packet pointer FIFOs 82 and 84 are independent.
The free lists 80 are in one physical memory, but logically contain pointers to its respective packet buffer.
The preceding, example describes a x8 5 Gig PICe port that can bifurcate to 2×4 5 Gig PCIe ports. The present embodiment can be adapted to other speeds, port segmentations for example quad-furcation, and protocols, to provide the benefit there from.
Numerous modifications, variations and adaptations may be made to the particular embodiments described above without departing from the scope patent disclosure, which is defined in the claims.
This application claims the benefit of U.S. Provisional Patent Application No. 60/870,868, filed on Dec. 20, 2006, by the same inventor, which is incorporated herein by reference in its entirety.
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Number | Date | Country | |
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20080174344 A1 | Jul 2008 | US |
Number | Date | Country | |
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60870868 | Dec 2006 | US |