Claims
- 1. A binary number substitution mechanism comprising:
- first and second storage arrays comprised of 2.sup.n n-bit storage locations and 2.sup.p p-bit storage locations respectively, said first and second storage arrays each including access means for simultaneously addressing one of the 2.sup.n storage locations of said first storage array and one of the 2.sup.p storage locations of said second storage array, and a total of n+p read-out signal lines for data stored in the storage locations of said first and second storage arrays;
- m input binary signal lines, said m input binary signal lines including an n-bit portion and a p-bit portion, the binary state of said m input binary signal lines being effective to represent 2.sup.m binary numbers;
- gate means, selectively and simultaneously interconnecting said n-bit portion of said m input binary signal lines to said access means of said first storage array and said p-bit portion of said input binary signal lines to said access means of said second storage array; and
- enabling means having an output signal connected to said gate means, and connected to said m input binary signal lines and responsive to certain ones of said binary number representations of said m input binary signal lines, for enabling said gate means whereby a substitute binary number manifestation is read out of said first and second storage arrays on said n+p read-out signal lines.
- 2. A binary number substitution mechanism in accordance with claim 1 wherein:
- the binary data stored in a particular one of said storage locations of one of said first or second storage arrays is caused to be different from the binary data stored in other of said storage locations of the same one of said first or second storage arrays when the number represented by said read-out signal lines would otherwise not be unique for two binary number representations of said m input binary signal lines.
- 3. A binary number substitution mechanism in accordance with claims 1, or 2 wherein said enabling means includes:
- a third addressable storage array, connected to said m input binary signal lines, comprised of 2.sup.m binary bit storage positions for storing a binary "0" or "1", each said bit storage position responsive to a particular binary number representation of said m input binary signal lines for generating said output signal when storing a particular one of said binary states.
Parent Case Info
This is a continuation, of application Ser. No. 269,146 filed June 1, 1981 now abandoned.
US Referenced Citations (16)
Non-Patent Literature Citations (1)
Entry |
Agrawala and Rauscher, Microprogramming: Perspective and Status, IEEE Transactions on Computers, vol. C-23, No. 8, Aug. 1978, pp. 817-837. |
Continuations (1)
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Number |
Date |
Country |
Parent |
269146 |
Jun 1981 |
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