Patent Application
20120011393
A computer-based device may include basic input output system (“BIOS”) programming. A processor in the device executes the BIOS programming to identify and test device hardware at startup, and to load and initiate an operating system, to interface with peripheral devices, etc.
The BIOS is generally stored in non-volatile semiconductor memory to allow for quick startup of the computer-based device. BIOS storage may feature in system reprogrammability to facilitate updating of BIOS programming. If the BIOS is corrupted, for example, if the stored BIOS programming is incorrect or damaged, then the device may be unable to boot.
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect, direct, optical or wireless electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, or through a wireless electrical connection. Further, the term “software” includes any executable code capable of running on a processor, regardless of the media used to store the software. Thus, code stored in memory (e.g., non-volatile memory), and sometimes referred to as “embedded firmware,” is included within the definition of software.
The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
Various computer-based devices store a basic input output system (“BIOS”) and associated programming and data in one or more non-volatile storage devices (e.g., FLASH memory devices) that are erasable and writeable in the device. Use of such storage facilitates introduction of new and/or different versions of the programming and data to the device. While generally robust, non-volatile storage devices are subject to corruption caused by a variety of internal and external conditions. For example, power instability while in the process of reprogramming may result in corruption or loss of data in the storage device. The device may be unable to startup properly if the BIOS or associated structures are damaged.
To mitigate the effects of a corrupted BIOS or associated data/programming stored in non-volatile memory, multiple copies of the BIOS may be stored. If device startup based on a given copy of the BIOS fails, a selection mechanism may cause the device to reattempt startup using a different copy of the BIOS.
BIOS programming is configured for operation with specific hardware, for example, a specific processor or processor type and specific logic (e.g., logic embodied in a chipset) configured for operation with an attached processor and associated device (e.g., memory, peripherals, etc). Some chipsets are configured to manage attached BIOS storage in a way that prohibits reprogramming of various regions of the non-volatile storage. Consequently, if such a non-writable region is corrupted or requires updating, the storage device cannot be reprogrammed in system.
Embodiments of the present disclosure include non-volatile storage configured to allow all regions of the storage to be reprogrammed in system when using a chipset configured to prohibit in system reprogramming of some regions of the storage.
The processor 102 may be a general-purpose processor, such as a processor produced by Intel Corporation, or a special-purpose processor such as a digital signal processor, a microcontroller, etc. Embodiments of the processor 102 generally include execution units (e.g., integer, fixed point, floating point, etc.), storage (e.g., registers, memory, etc.), instruction decoding and/or scheduling logic, clock systems, and interconnect systems (e.g., buses). The processor 102 executes instructions fetched from a memory or other computer-readable medium.
The chipset 104 provides an interface between the processor 102 and various peripheral systems and devices. In some embodiments, the chipset 104 may include a northbridge and a southbridge. Embodiments of the chipset 104 may implement the northbridge and southbridge as separate components or as a single component. Some embodiments may combine the processor 102 and the chipset 104 into a single component.
The volatile memory 106 may be, for example, dynamic random access memory (e.g., DRAM, DDRAM, SDRAM, etc), static random access memory, or the equivalent. The volatile memory 106 may be interfaced to the processor 102 via a memory controller of the chipset 104 as shown, or, in embodiments of the processor 102 including a memory controller, may be interfaced directly to the processor 102.
Disk 110 provides storage for program and data elements apart from the BIOS Storage 114. Disk 110 typically comprises a magnetic hard drive, but more generally may comprise a FLASH drive, optical drive, or other non-volatile storage medium.
Display 108 provides visual information to a user. A Liquid Crystal Display, Cathode Ray Tube display, plasma display, Organic Light Emitting Diode display, electroluminescent display, projection display, or other display technology suitable for displaying text and/or graphics may be employed.
The miscellaneous peripherals 112 include input/output devices (e.g., keyboard, mouse, trackball, touchpad, touchscreen, etc), audio transducers (e.g., microphone, speakers), network interfaces, etc. The chipset 104 may include interfaces dedicated to a peripheral (e.g., audio input/output), and/or general-purpose interfaces (e.g., universal serial bus, peripheral component interface, etc) for connecting with the peripherals 112.
The chipset 104 may include a controller 124 that manages access to the BIOS storage 114. The controller 124 may be configured to prohibit write accesses to various regions of the BIOS storage 114, and to allow write accesses to other regions. In some embodiments, the controller 124 is implemented as processor, similar to the processor 102, that executes software programming.
The BIOS storage 114 provides non-volatile memory for storing programs and data. In some embodiments, a BIOS program 120 used to boot the device 120, device 120 configuration descriptors 116, other programs (e.g., programming executed by the controller 124), and/or platform data 118 reserved for general information use are included in the BIOS storage 114. In some embodiments, the BIOS storage 114 may be interfaced to the chipset 104 via a Serial Peripheral Interface Bus (“SPI”).
In some devices, the controller 124 restricts descriptor 116 accesses to read accesses only. Embodiments of the present disclosure advantageously allow descriptors 116 to be written by the processor 102 even though the controller 124 restricts descriptor 116 accesses to reading. Embodiments provide this advantage along with redundancy for descriptors 116, BIOS Program 120, and other programs 122 by configuration of the platform data 118 as described herein, and by inclusion of the selection logic 126. The selection logic 126 includes chip select routing 130 and control logic 128, and provides control of BIOS storage selection independently of the controller 124.
In some embodiments, the organization of the storage regions included in the BIOS storage 114 is constrained by use of the chipset 104, wherein the controller 124 is configured for operation based on a predetermined organization of the storage regions 216, 218, 220, 222 in the BIOS storage 114. In some embodiments, the arrangement of regions 216, 218, 220, and 222 is constrained as illustrated in
Thus, the totality of the BIOS storage 114 is allocated to the illustrated memory regions 216, 218, 214, 222, 220, which may be referred to as the “active” regions. The controller 124 may be configured to operate based on these regions. Thus, the controller 124 may be configured to retrieve a BIOS 120 for execution by the processor 102 from the BIOS region 220 located at the uppermost addresses of the BIOS storage 114. Embodiments of the controller 124 may also bar the processor 102 from writing to the descriptors region 216 (i.e., the descriptors 116 may be read-only).
In order to provide improved device 100 reliability, embodiments of the present disclosure arrange the storage regions 216, 218, 214, 222, 220 across the two BIOS storage devices 202, 204 to provide redundancy for all storage regions and to allow updating of the descriptors 116. Embodiments provide such redundancy by allocating to the platform data region 218 an amount of storage equal to the storage capacity provided for use by each of the BIOS storage devices 202, 204. Thus, if each of device 1202 and device 2204 are configured to provide 4 MB of storage, then 4 MB of storage are allocated to the platform data 218 region. Because the platform data region 218 is disposed immediately above the descriptors region 216, the platform data region 218 extends into the BIOS storage device 2204 for a length equal to the length of descriptors region 216 (e.g., 4 KB). Thus, in embodiments of the present disclosure, the platform data region 218 occupies all but the descriptors 216 region of the BIOS storage device 1202, and occupies a lowest addressable portion of the BIOS storage device 2204 of size equal to the descriptors region 216.
The platform data region 218 is subdivided into a number of sub-regions 206-212, which may be referred to as “reserve” regions 206-212. Each reserve region is sized and positioned to provide redundancy for a corresponding active region 216, 214, 222, 220. Thus, the descriptors region 206 provides redundancy for the descriptors 216, the BIOS 208 provides redundancy for the BIOS 220, the controller program 210 provides redundancy for the controller program 222, and the optional region 212 provided redundancy for the optional region 214.
As explained above, the controller 124 may be configured to access a given region only at a specified storage location. For example, the controller 124 may retrieve the BIOS 120 for execution only from the uppermost address space of the BIOS storage 114 (i.e., the BIOS region 220). Consequently, the controller 124 may be unable to retrieve for execution the BIOS 208 because the BIOS 208 is not located at the top of the BIOS storage 114 address space.
Embodiments allow BIOS storage device 1202 and BIOS storage device 2204 of switch positions in the BIOS storage 114 address space. By switching the address positions of the devices 202 and 204, a BIOS program 120 previously positioned in the BIOS region 208 is repositioned at the top the BIOS storage 114 address space, and the descriptors 116 previously positioned in the descriptor region 206 are repositioned at the bottom the BIOS storage 114 address space. That is, the data previously positioned in reserve regions 206-212 will respectively occupy the address spaces assigned to the active regions 216, 220, 222, and 214, and the data previously disposed in the active regions 216, 220, 222, and 214 will be repositioned in the address space reserved for the reserve regions 206-212. Explained in a alternative manner, the storage regions 206-222 may be viewed as static address ranges, and information stored in device 1202 and device 2204 change locations across the address ranges when the address positions of the devices 202 and 204 are swapped.
Thus, embodiments provide redundancy for all regions of the BIOS storage 114, and allow the processor 102 to write the descriptors 116 by writing to corresponding fields of the descriptors region 206, which will be positioned at the lowermost addresses of the BIOS storage 114 after the devices 202 and 204 are swapped in the address space.
The control logic 128 includes routing state logic 302 and timer 304. Routing state logic 302 controls which of the chip selects 308, 310 is routed to each device 202, 204. In a first state (e.g., state “0”), assertion of the chip select 308 may activate device 1202, and assertion of the chip select 310 may activate device 2204. Conversely, in a second state (e.g., state “1”), assertion of the chip select 310 may activate device 1202, and assertion of the chip select 308 may activate device 2204.
The routing state logic 302 is driven by signals provided from the controller 124 and the timer 304. The timer 304 may be watchdog timer configured to change the routing state if the timer 304 expires before the processor 102 properly executes a retrieved BIOS 120 (e.g., before the processor 102 properly completes BIOS 120 execution and starts an operating system). In some embodiments, the routing state logic is a flip-flop and input data and clock (both data and clock shown as signal 316) for the flip-flop are provided by the timer 304. The timer 304 provides the clock and data signals 316 to toggle the state value responsive to the timer 304 expiring. In some embodiments, the controller 124 provides an enable signal 314 allowing the routing state to change only when the processor 102 is in a reset state. In some embodiments, the timer 304 may be implemented as an auxiliary processor or board management device and may include logic allowing the chip select routing state to be changed based on a command or trigger signal received from the processor 102.
In block 402, the device 100 is operating and the selection logic 126 is configured to route chip selects 308, 310 provided from the controller 124 to the BIOS storage devices 202, 204. Based on the chip select routing state, the controller 124 retrieves a first BIOS for execution by the processor 102. The BIOS retrieved for execution is located in the BIOS region 220 disposed at the uppermost addresses of the BIOS storage 114. In some embodiments, the BIOS retrieved from the BIOS storage 114 is moved to the volatile memory 106 for execution by the processor 102.
In block 404, the device 100 determines whether an error has occurred during BIOS execution. For example, a check value (e.g., a cyclic redundancy check) associated with the retrieved BIOS may indicate that the BIOS is corrupt, the timer 304 may time out awaiting a timer reset from the processor 102 indicating successful BIOS execution, etc. If BIOS execution is successful, method is complete.
If BIOS execution is unsuccessful, then in block 406 the chip select routing logic 130 is reconfigured to swap the positions of the BIOS storage devices 202, 204 in the BIOS storage 114 address space. The reconfiguration is related to a change in routing state 302 that may be in response to signals provided from the timer 304 after the timer 304 expires. The chip select routing logic 130 reconfiguration swaps the destinations of the chip select signals 308, 310 provided from the controller 124, thereby causing the controller 124 to fetch a different instance of the BIOS for execution by the processor 102 during the next BIOS retrieval.
In block 408, a device 100 reset is performed and the controller 124 retrieves from BIOS storage 114 a second BIOS for execution. The second BIOS retrieved in block 408 may different from the first BIOS retrieved in block 402, and may be a BIOS that was disposed in the BIOS region 208 prior to swapping the destinations of the chip select signals. In some embodiments, the controller 124 moves the second BIOS into the volatile memory 106 from where the processor 102 fetches and executes the instructions of the second BIOS.
In block 410, the processor 102 writes BIOS instructions (e.g., updated BIOS) to the BIOS storage region 208 disposed in the platform data 218. Information overwritten in the BIOS storage region 208 was located in the BIOS storage region 220 prior to reconfiguring the chip selects. The processor 102 may also write descriptor data to the descriptor region 206 disposed in the platform data 118, and/or may write data to the regions 210 and/or 212. The BIOS and descriptors disposed in the platform data region 218 will become the active BIOS and descriptors following a next reconfiguration of the chip selects via a subsequent change in state of the routing state logic 302.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
