The invention relates generally to integrated circuit fabrication processes and structures formed according to the processes, and more specifically to fabrication processes for forming a vertical PNP transistor with reduced collector-substrate capacitance and vertical PNP transistors formed according to the process.
A plurality of integrated circuits are formed on a semiconductor wafer according to a sequence of process steps, collectively referred to as a wafer fabrication process. Each integrated circuit comprises a semiconductor substrate and semiconductor devices, such as transistors (e.g., bipolar junction transistors (BJTs) and metal-oxide semiconductor field effect transistors (MOSFETs)) formed from doped regions within the substrate. Interconnect structures overlie the semiconductor substrate for electrically connecting the doped regions to form electrical devices and circuits implementing desired electrical functions. Conventional interconnect structures comprise substantially horizontal dielectric layers separating overlying and underlying substantially horizontal conductive structures comprising conductive traces or runners. Vertical conductive vias or plugs in the dielectric layers connect the horizontal conductive structures in the overlying and underlying conductive layers. The various layers and regions are formed and patterned using conventional fabrication techniques, such as oxidation, implantation, deposition, epitaxial growth, lithography, developing, etching, and planarization.
The sequence of process steps must be carefully designed and executed to ensure that the devices are properly formed and that processes associated with later steps do not adversely affect previously-formed structures, as such adverse effects can impair device operation, lowering fabrication yields and increasing costs. It is also desired to limit the number of mask steps to lower fabrication costs. Thus semiconductor manufactures desire to implement a fabrication process flow that produces properly operable transistors (e.g., PNP and NPN BJTs and MOSFETs) and other devices with a high fabrication yield.
A BJT comprises three adjacent doped semiconductor regions or layers having an NPN or a PNP doping configuration. A middle region forms a base and two end regions form an emitter and a collector. Typically, the emitter has a higher dopant concentration than the base and the collector, and the base has a higher dopant concentration than the collector. Generally, the BJT can be operated as an amplifier (for example, to amplify an input signal supplied between the base and the emitter, with the output signal appearing across the emitter/collector) or as a switch (for example, an input signal applied across the base/emitter switches the emitter/collector circuit to an opened or a closed state.
A MOSFET, which differs in structure and operation from a BJT, comprises source and drain regions of a first dopant type formed in a tub or well of a second dopant type. A voltage applied to a gate disposed above the well between the source and drain changes a conductivity of a channel region between the source and the drain, permitting current flow through the channel.
BiCMOS integrated circuits comprise both BJTs and CMOS (complementary MOSFETs, i.e., a p-type MOSFET (PMOSFET) and an n-type MOSFET (NMOSFET)) formed on the same substrate with the fabrication process steps for both devices integrated into one fabrication sequence. BiCMOS circuits have many uses in the electronics industry, combining the high power and fast switching speeds of bipolar devices with the high density and low power consumption of MOSFETS. The multitude of applications for BiCMOS devices has encouraged the development of faster and denser BiCMOS integrated circuits with higher current capacity.
There are several known semiconductor fabrication processes for forming the three doped layers of a BJT and several transistor architectures can be formed according to such processes. The fabrication of NPN BJTs is typically optimized for a given process and the PNP BJTs can be “free,” i.e., certain masks are modified to form PNP BJT structures, but no additional process steps are required. A lateral BJT structure, where the current flows laterally from the emitter to the collector is one type of “free” PNP BJT.
A common vertical BJT planar structure (where the current flows perpendicular to a plane of the substrate) comprises stacked NPN or PNP regions formed by successive dopant implants into a substrate. Significant performance enhancements are achieved by forming the emitter from a polysilicon layer. For example, using a polysilicon emitter allows greater control over the emitter-base doping profile. Further performance enhancements are achieved by using two layers of polysilicon (referred to as a double-polysilicon BJT) one polysilicon layer for the emitter and the other for an extrinsic base. This architecture reduces base resistance and collector-base capacitance, among other advantages.
In one embodiment the PNP BJT is fabricated on a p-type substrate, requiring the use of an n-type layer in the substrate to isolate the p-type substrate from the BJT p-type collector. A parasitic capacitance is formed across the reverse-biased junction between the collector and the isolating structure, referred to as a collector-substrate capacitance or a collector-n-isolation region capacitance Ccs. As is known, this capacitance degrades high-frequency BJT performance in analog applications and lowers BJT switching speed in digital applications.
A cross-sectional illustration of such a prior art vertical PNP BJT 600 is illustrated in
Doped regions of the PNP BJT 600 are formed within a substrate 608 and isolated by isolation regions 610. An n-type isolation sinker region 611 cooperates with an n-type isolation triple well region 612 to form a triple well isolation structure.
A collector region is indicated generally by a reference character 615, including a highly-doped collector contact surface region 614 within a p-type sinker 618. Since a subcollector region 620 is deep within the substrate 608 (in an embodiment having a high breakdown voltage the subcollector region can be more than 1 micron below an upper surface of the substrate) the collector contact surface region 614 cannot make satisfactory contact with the subcollector region 620, necessitating use of the p-type sinker 618. The collector 615 may also include an optional p-type SIC (selectively implanted collector) region 622.
A polysilicon emitter 624 overlies and is separated from an n-type intrinsic base 626 by a dielectric material layer 627. Transistor action occurs at the junction between the intrinsic base and the emitter. The intrinsic base 626 contacts an n-type extrinsic base 628, a heavily-doped region that links the intrinsic base 626 to later formed conductive plugs (base contacts) in electrical communication with the extrinsic base 628.
An n-type isolation contact surface region 634 within the n-type sinker region 611 is biased to isolate the PNP collector regions from the p-type substrate 608.
Contact to the emitter 604 is made on a top surface of the emitter polysilicon 604 and contact to the collector is made through the collector contact surface region 614.
The doped regions and contacts of the PNP BJT 600 are fabricated according to known fabrication processes.
The collector-n-isolation region parasitic capacitance Ccs between the subcollector region 620 and the isolation region 612 is illustrated in phantom in
The sidewall capacitance can be reduced by employing deep trench isolation in which a deep trench (not shown in
In yet another prior art PNP BJT the isolation triple well region is implanted, an epitaxial layer is grown over the isolation region and the collector is implanted in the epitaxial layer. This process controls the collector depth to reduce the distance between the collector and the underlying isolation region, reducing the capacitance between these two structures. Disadvantageously, this process requires two implant steps and the epitaxial growth step tends to introduce defects into the grown silicon.
In another PNP BJT embodiment (not illustrated) the collector is formed proximate a buried silicon dioxide layer (e.g., a silicon-on-insulator layer) to reduce the collector-n-isolation region parasitic capacitance. Use of both the buried oxide layer and the deep oxide trenches provides the lowest capacitance values for Ccs and Cs.
In yet another alternative, an n-type substrate is substituted for the p-type substrate, i.e. the PNP BJT is formed in an n-type substrate. Although this approach reduces the PNP BJT collector-isolation region parasitic capacitance by eliminating the n-isolation region, (the revere biased pn junction between the p-type collector and the n-type substrate provides suitable isolation). In an application where an NPN BJT is also fabricated on the substrate (a typical configuration), the problems associated with the parasitic capacitance are merely shifted from the PNP BJT to the NPN BJT. Further, a p-type substrate is generally preferred for BiCMOS circuits in which MOSFETs and BJTs are formed.
It is therefore desired to identify process techniques and structures that further reduce the collector-n-isolation region capacitance Ccs.
According to one embodiment, the present invention comprises a method for forming a bipolar junction transistor. The method comprises providing a semiconductor layer having a surface, forming spaced-apart first and second collector regions in the semiconductor layer, forming a buried isolation region below a lower surface of the first and the second collector regions and implanting a subcollector comprising first and second end portions extending from a body portion, the first and the second end portions overlapping the respective first and second collector regions, wherein the first and the second end portions are shallower, relative to the surface, than the body portion.
According to another embodiment of the invention, a bipolar junction transistor comprises a semiconductor substrate having a surface, spaced apart first and second collector regions in the substrate and a third collector region having a body portion and first and second end portions extending therefrom, the first and second end portions overlapping the respective first and second collector regions, wherein the first and second end portions are shallower relative to the surface than the body portion.
The present invention can be more easily understood and the advantages and uses thereof more readily apparent when the following detailed description of the present invention is read in conjunction with the figures wherein:
In accordance with common practice, the various described features are not drawn to scale, but are drawn to emphasize specific features relevant to the invention. Like reference characters denote like elements throughout the figures and text.
Before describing in detail exemplary methods and apparatuses related to fabrication of a vertical PNP BJT in a BiCMOS process and structures formed according to the process to reduce the parasitic collector-n-isolation region capacitance, it should be observed that the present invention resides primarily in a novel and non-obvious combination of elements and process steps. So as not to obscure the disclosure with details that will be readily apparent to those skilled in the art, certain conventional elements and steps have been presented with lesser detail, while the drawings and the specification describe in greater detail other elements and steps pertinent to understanding the invention. The illustrated process steps are exemplary, as one skilled in the art recognizes that certain independent steps illustrated below may be combined and certain, steps may be separated into individual sub-steps to accommodate individual process variations.
The teachings of the present invention are applicable to silicon PNP and NPN BJTs and to heterojunction bipolar junction transistors (HBTs), wherein the three material regions of the BJTs and the HBTs comprise silicon, silicon-germanium, gallium-arsenide or other suitable materials. The description below refers to an exemplary silicon PNP BJT to describe the invention.
A vertical PNP may be fabricated as follows with reference to the process sequence depicted in
Structural elements as illustrated in
P-type dopants implanted through a suitably patterned photoresist structure form p-type sinker regions 19. N-type dopants implanted through a suitably patterned photoresist structure form n-type sinker isolation regions 32. An n-type triple well isolation region 36 is formed by implanting n-type dopants through an appropriately patterned photoresist structure. Exemplary implant conditions for forming the triple well isolation region 36 comprise phosphorous implanted at 1200 keV with a density of 4E12 per cm3. Spaced-apart lateral ends 36A of the n-type triple well isolation region 36 overlap with lower ends of the n-type sinker isolation regions 32 to form an n-type triple well isolation tub surrounding the p-type sinker regions 19 and other later-formed PNP BJT structures.
Structures 45 overlying isolation structures 16A and 16B are formed by depositing and patterning one or more material layers. In an embodiment where MOSFETS are formed in the substrate 12, the structures 45 can each comprise a MOSFET gate stack. Other suitable materials (including dielectric materials) may be used to form the structures 45. The gate stacks are formed by blanket depositing a gate oxide layer, polysilicon layer (doped in situ or by implant doping) and a tungsten layer. The polysilicon and tungsten layers ate etched according to a pattern in an overlying patterned photoresist layer or, more commonly in an overlying hard mask layer. In the latter case, each gate stack comprises a polysilicon layer, a tungsten silicide layer (formed from the polysilicon and tungsten) and a hard mask layer. In one embodiment the gate stacks, and thus the structures 45, are about 300 nm thick.
Through a patterned photoresist structure 70 (see
The structures 45 overlying the isolation structures 16A and 16B reduce the implant range of the implanted subcollector 72 over portions of the subcollector 72 underlying the structures 45, forming end regions 72A overlapping the p-type sinker regions 19 and spaced vertically apart from the n-type triple well isolation region 36. The implant range is reduced by a distance about equal to a thickness of the structures 45.
This spaced-apart end regions 72A in the subcollector 72 reduce the collector-n-isolation region capacitance since the capacitance is inversely proportional to the distance between the charged regions of the reverse biased junction formed between the p-type collector and the n-type isolation region. This feature also reduces the collector resistance because the subcollector end regions 72A are each closer to a respective collector contact surface region formed later in a surface of the sinker regions 19.
Continuing with
The teachings of the present invention can be applied to the formation of a PNP BJT in various types of integrated circuits, including a BiCMOS integrated circuit including both BJTs and MOSFETs. In this application, a spacer oxide layer is formed over a substrate surface to form spacers adjacent the MOSFETs gate stacks. Such a spacer oxide layer 82 is illustrated in
According to an appropriately patterned mask, the polysilicon layer 150 is etched to form a PNP emitter 150A. See
N+ extrinsic base regions 236 are formed in spaced-apart end regions of the base 74 by implant doping through a patterned mask. N+ high-dopant density contact surface regions 238 are formed in the sinker isolation regions 32.
Using a patterned implant mask, high-dopant density collector surface regions 264 are formed in a surface of the PNP collector regions 19 as illustrated in
An edge 270 of each one of the structures 45 is preferably located to avoid overlap with the extrinsic base regions 236 (as any overlap can detrimentally affect the implant doping that forms the extrinsic base regions 236) and also to maintain a suitable base-collector breakdown voltage, i.e., avoid reducing a distance between the subcollector 72 and the base 74 that lowers the base-collector breakdown voltage. A width of the structures 45 must also consider a width of the underlying isolation structures 16A and 16B.
An edge 280 of each one of the structures 45 is preferably located within an opening of a subcollector mask through which the subcollector 72 is formed, ensuring that a distance between the subcollector 72 and the n-isolation region 36 is greater at the end portions 72A than at other regions of the subcollector 72.
A silicon dioxide layer (not shown) is formed (typically according to a high-density plasma deposition process) to encapsulate the substrate 12 and the structures formed therein to prevent the dopant atoms from evaporating from the semiconductor material during a subsequent anneal process. The substrate 12 is annealed to repair crystal lattice damage resulting from collisions between the implanted n-type and p-type dopants and the lattice atoms and to electrically activate the implanted dopants.
Conventional processing steps (referred to as backend process steps) are performed to passivate the upper surface of the substrate 12, fabricate interconnect structures and package the device. A first dielectric layer and a first conductive layer are deposited overlying the substrate 12 to form a first layer interconnect (not shown in the Figures). The first level interconnect structures comprise conductive plugs formed in the dielectric layer for contacting the PNP emitter 150B, the PNP extrinsic bases 236, the high-dopant density contact surface regions 238 in the sinker isolation regions 32 and the PNP high-dopant density collector contact surface regions 264.
Use of the structures 45 also ensures that the base implant (i.e., the base 74 implanted as described in conjunction with
In an embodiment where the structures 45 comprise MOSFET gate stacks, the polysilicon material layer in the gate stack can be connected to ground, forming a shield or field plate to limit cross talk or electrical interference between devices.
The process according to the present invention for decreasing the capacitance between the PNP collector and the n-isolation region is easily adaptable to current fabrication process flows as no additional processing steps are required. Only different mask configurations are required. For example, although described with reference to a PNP BJT emitter formed from a polysilicon layer and an implanted base, the teachings of the present invention can also be applied to a PNP BJT comprising an extrinsic base and an emitter each formed from separate polysilicon layers, and can be applied to a PNP BJT comprising an implanted emitter and an implanted base.
While the process of the invention has been described with reference to a PNP BJT having a single polysilicon emitter region (150B) intermediate extrinsic base regions (236), the teachings of the present invention can also be applied to a BJT having two spaced-apart emitter regions with a base region intermediate thereto as further described and claimed in commonly owned patent application entitled Processes for Forming Bipolar Junction Transistors and Bipolar Junction Transistors Formed According to the Processes, (attorney docket number Chen 21-1-15-7-9/075903-464) filed on ______ and assigned application number ______, the teachings of which are herein incorporated by reference.
The process of the present invention can also be applied to the fabrication of an NPN BJT in an n-type substrate for reducing capacitance between the NPN BJT collector and the underlying p-type isolation region and the fabrication of an NPN BJT in an n-type well formed in a p-type substrate. An NPN BJT 360 of
The process for forming the PNP transistor of the present invention can also be applied to a complementary BiCMOS process and structures formed according to the process. Generally, it will be appreciated that one can fabricate the novel device independently of its application to any specific process or in conjunction with the fabrication of other devices in the substrate.
It should also be recognized that while the embodiment described utilizes compounds or elements commonly employed in today's technology as dopants, isolation layers and the like, it is possible to substitute other materials that function in the same manner for the preferred materials of today's technology.
Although the present invention has been described with reference to preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalent elements may be substituted for the elements thereof without departing from the scope of the invention. The scope of the present invention further includes any combination of elements from the various embodiments set forth herein. In addition, modifications may be made to adapt a particular situation to the teachings of the present invention without departing from its essential scope. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments failing within the scope of the appended claims.
Filing Document | Filing Date | Country | Kind | 371c Date |
---|---|---|---|---|
PCT/US2006/021396 | 6/2/2006 | WO | 00 | 10/13/2009 |