Patent Application
20140173381
Noise-Predictive Maximum Likelihood Detection (“NPMLD”) is an advanced digital signal-processing method that can be used with magnetic data storage systems, such as tape drives, hard disk drives, etc., that operate at high linear recording densities. Additionally, NPMLD can refer to a family of sequence-estimation data detectors, which arise by embedding a noise prediction/whitening process into the branch metric computation of a Viterbi algorithm. Relatively reliable operation of the prediction/whitening process can be achieved by using hypothesized decisions associated with the branches of a trellis on which the Viterbi algorithm operates, as well as tentative decisions corresponding to a path memory associated with each trellis state. The NPMLD detectors can thus be viewed as a family of reduced-state sequence-estimation detectors offering a range of implementation complexities, where complexity is essentially governed by the number of detector states. As such, NPMLD can be used for retrieving data recorded on the magnetic medium since the data may be read back as a weak and noisy analog signal by the read head. Because the goal of NPMLD is to minimize the influence of noise in the detection process, it allows recording at higher areal densities than other detection schemes.
Bit errors coming out of a data detector (e.g., an NPMLD detector) can be corrected by using an Error Correction Code (ECC) like a Reed-Solomon code, for example. However, the ECC cannot correct bit errors if the number of bit errors is larger than a certain threshold (i.e. if the number of bit errors is larger than an error correction capability). Therefore, an efficient bit error reduction scheme is required after the data detector and before the ECC.
In a traditional method, a post-Viterbi processing is applied at the output of the NPMLD to correct some of the dominant error events. Post processing is a low-complexity operation, usually employed after data detection algorithms to improve Bit Error Rate (BER) performance of magnetic recording systems. Post processing has been shown to be helpful when the distributions of error events at the output of the NPMLD are not even and the distributions are used at the post processor. In other words, some dominant error events are identified first, and then the entire post processor is designed to detect and correct those dominant error events. One of the advantages of post processing is its low complexity. In particular, it has been found that the use of such an approach usually leads to only a moderate increase in implementation complexity. However, post processors are often sub-optimal solutions and are usually not robust, i.e. the post processors attempt to correct dominant error events, but at the expense of leading to other unwanted error events that are not originally part of the NPMLD output. Although some threshold-based post processors have been introduced without using any extra redundancy, they are not practical. Additionally, such threshold-based post processors have also been found to be unreliable and often they have not lead to improved performance. Thus, post processing schemes based on Error Detection Codes (sometimes referred to herein as “EDC” or “EDCs”) became more popular and were used in various ways at the expense of a slight penalty at code rate.
The present invention is directed to a method for reducing the number of error events in a transmitted data stream. In certain embodiments, the method comprises the steps of (i) generating at least a first most probable sequence and a second most probable sequence with a detection algorithm; (ii) determining if a first correctable error occurred in the first most probable sequence with an EDC decoder; and (iii) determining if a second correctable error occurred in the second most probable sequence with the EDC decoder.
It should be noted that although such embodiments of the method disclosed with regard to the present invention are described as merely including the step of generating at least a first most probable sequence and a second most probable sequence with a detection algorithm, the method can be designed to generate greater than two most probable sequences with the detection algorithm. More particularly, the proposed method and detection algorithm can maintain and/or generate a list of the N most probable sequences (per state of a trellis) based on the observation that most of the error events can be recovered by finding a set of most likely paths, including the maximum likelihood path. Additionally, as provided herein, a periodic decision-making process is employed for every period, i.e. for every P bits of data, based on error detection codes in order to detect and correct at least some of the error events.
In one embodiment, the steps of determining if a first correctable error occurred and determining if a second correctable error occurred are performed substantially simultaneously.
Additionally, in some embodiments, the step of determining if a first correctable error occurred includes the EDC decoder having a first parity check code that is used to evaluate the first most probable sequence. Further, in such embodiments, the step of determining if a second correctable error occurred can include the EDC decoder having a second parity check code that is used to evaluate the second most probable sequence. In one such embodiment, the step of determining if a first correctable error occurred further includes the first parity check code utilizing three parity bits that are added to a first portion of the transmitted data stream to evaluate the first most probable sequence. Moreover, in such embodiment, the step of determining if a second correctable error occurred can further include the second parity check code utilizing three parity bits that are added to a second portion of the transmitted data stream to evaluate the second most probable sequence.
In another embodiment, the step of determining if a first correctable error occurred includes the EDC decoder having a first cyclic redundancy check code that is used to evaluate the first most probable sequence. In such embodiment, the step of determining if a second correctable error occurred can also include the EDC decoder having a second cyclic redundancy check code that is used to evaluate the second most probable sequence.
In one embodiment, the method as described herein above can further comprise the step of separating the transmitted data stream into a plurality of data chunks, with each data chunk including a specified number of bits. In such embodiment, the step of generating includes the detection algorithm generating at least a first most probable sequence and a second most probable sequence for each data chunk.
Additionally, in certain embodiments, the method as described herein above further comprises the steps of computing a plurality of path metrics for the transmitted data stream, and selecting a first q smallest path metrics out of the first most probable sequence and the second most probable sequence with a Q value selector. In one such embodiment, the step of determining if a first correctable error occurred includes evaluating the first q smallest path metrics with the EDC decoder to determine if a first correctable error occurred in the first most probable sequence. Additionally, in such embodiment, the step of determining if a second correctable error occurred can further include evaluating the first q smallest path metrics with the EDC decoder to determine if a second correctable error occurred in the second most probable sequence. Moreover, in one embodiment, the method can further comprise the step of updating the plurality of path metrics based on the evaluation of the first q smallest path metrics by the EDC decoder.
Additionally, the present invention is further directed to a method for detecting bit errors in a transmitted data stream, the method comprising the steps of (i) generating at least a first most probable sequence and a second most probable sequence with a detection algorithm; (ii) computing a plurality of path metrics for the transmitted data stream; and (iii) selecting a first q smallest path metrics out of the first most probable sequence and the second most probable sequence with a Q value selector.
Further, in another embodiment, the present invention is also directed to an error correction system for reducing the number of error events in a transmitted data stream, the error correction system comprising a detection algorithm that generates at least a first most probable sequence and, a second most probable sequence; and an EDC decoder that determines (i) if a first correctable error occurred in the first most probable sequence, and (ii) if a second correctable error occurred in the second most probable sequence.
The novel features of this invention, as well as the invention itself, both as to its structure and its operation, will be best understood from the accompanying drawings, taken in conjunction with the accompanying description, in which similar reference characters refer to similar parts, and in which:
As provided in detail herein, a List-Noise Predictive Maximum Likelihood Detection (List-NPMLD) algorithm (also referred to herein as a “detection algorithm”) based on periodic insertions of parity check codes and cyclic redundancy check (CRC) codes is introduced for magnetic recording channels in a bit error detection and correction system (also sometimes referred to herein as an “error correction system”). The detection algorithm is an increased performance sequence estimation algorithm which preserves one or more of the desirable properties of a conventional NPMLD, such as embedded noise prediction.
In particular, the proposed detection algorithm keeps a list of candidate paths (N most probable sequences (or candidates) per state of a trellis) based on the observation that most of the error events can be recovered by finding a set of most likely paths, including the maximum likelihood path. As provided in detail herein, a periodic decision-making process is employed for every period (i.e. for every P bits of data) based on error detection codes in order to detect and correct at least some of the error events.
For example, for representative recording channel and signal-to-noise ratio (SNR) conditions, when using N=3 (i.e. three most probable sequences) and P=200 (i.e. periods that include two hundred bits of data), the List-NPMLD algorithm provided herein can correct approximately 92% of the error events at the output of a conventional NPMLD algorithm. Additionally, the List-NPMLD algorithm embodiments described herein do not change the distributions of error events and hence can easily be combined with a traditional post processing method that targets a specific set of dominant error events. Therefore, as described herein, the List-NPMLD algorithm can either be considered as an alternative to traditional post processing methods, or as a complementary method that can be combined with other post processing methodologies. Unlike traditional post processing methodologies, the detection algorithm of the present invention utilized with the error correction system does not need to know the error event distribution. Moreover, if the EDC works perfectly, it does not add any new error events caused by false corrections. Additionally, as discussed herein, simulation results show that the proposed List-NPMLD algorithm combined with an EDC can improve BER performance at magnetic recording channels.
It should be noted that the present detection algorithm is useful with various high density data recording channels, such as a tape drive system, e.g., an LTO Gen7 tape drive, a hard disk drive system, or other suitable high density data recording channels. Additionally, the proposed detection algorithm can also be used in other suitable applications.
As used herein, a Viterbi algorithm is a dynamic programming algorithm for finding the most likely sequence of hidden states—called the Viterbi path—that results in a sequence of observed events. Additionally, an EDC is a set of suitable functions that add fixed-length redundancies (tags) to a message far error detection. Since the receiver knows the functional operation of the EDC, the tags can be recomputed at the receiver. Then the tags are compared with the original tags to decide whether there has been any change in the original message (i.e. bit errors) during transmission. If the comparison indicates a success (i.e. no bit errors), the EDC decoder 14 flags ‘pass’; otherwise, the EDC decoder 14 flags ‘failure’.
Upon detection of an error during any given data transmission operation (a “data error”), the detection algorithm 12 determines the most probable paths or most probable sequences 16 in which a correctable error may have occurred. In the embodiment shown in
At the output of the List-Viterbi detection algorithm 12, the EDC (i.e. parity check code, CRC code) decoders 14 decide which sequence is valid (e.g., passing parity check or CRC) because an error-free sequence will pass the parity check. Stated in another fashion, at the output of the detection algorithm 12, each most probable sequence 16 is evaluated via a parity check, i.e. the first most probable sequence 16(1) is evaluated via a first parity check 18(1), the second most probable sequence 16(2) is evaluated via a second parity check 18(2), and so on, up to and including the Nth most probable sequence 16(N) being evaluated via an Nth parity check 18(N). Additionally, in one embodiment, each of the parity checks 18(1)-18(N) for each of the most probable sequences 16(1)-16(N), respectively, are performed substantially simultaneously. As utilized herein, parity checking refers to the use of parity bits, which are added to many or all data units that are transmitted, to check that the data has been transmitted accurately. The parity bits are bits that are added to increase the likelihood or ensure that the number of bits with the value of one in any given set of bits is either even (“even parity”) or odd (“odd parity”). Further, a selector 20 of the error correction system 10 sends out one sequence that passes the corresponding parity check as a final decision. With this design, the final decisions are already verified to be substantially or completely error-free as long as the EDC decoding was successful.
It is recognized that although the EDC decoders 14 are described in detail herein with the use of parity check codes, the EDC decoders 14 can also be used effectively utilizing CRC codes, and there is no intent to limit the scope and breadth of the present invention due to the more detailed description in relation to the parity check codes.
Additionally, it should be noted that, as shown in
In one embodiment, three parity bits (i.e. three-bit tags) are added to the input data for dominant error event detection. In this embodiment, the parity bit is a bit that is added to increase the likelihood or ensure that the number of bits with the value of one in any given set of bits is either even or odd, depending on the type of parity chosen. For example, for even parity, if a given set of data bits (i.e. a given set of 0's and 1's) includes an odd number of 1's, then the parity bit chosen will be a 1, so that the total number of 1's is even. Additionally, for even parity, if a given set of data bits includes an even number of 1's, then the parity bit chosen will be a 0, so that the total number of 1's remains even. Conversely, for odd parity, if a given set of data bits includes an odd number of 1's, then the parity bit chosen will be a 0, so that the total number of 1s remains odd. Further, for odd parity, if a given set of data bits includes an even number of 1's, then the parity bit chosen will be a 1, so that the total number of 1's is odd. Thus, for performing a parity check utilizing even parity, (i) if the total number of 1's in a given set of data bits (including the parity bit) is even, then no parity error has occurred during transmission of the data; and (ii) if the total number of 1's in a given set of data bits (including the parity bit) is odd, then that is evidence that a parity error occurred during transmission. Conversely, for performing a parity check utilizing odd parity, (i) if the total number of 1's in a given set of data bits (including the parity bit) is odd then no parity error has occurred during transmission of the data; and (ii) if the total number of 1's in a given set of data bits (including the parity bit) is even, then that is evidence that a parity error occurred during transmission.
Referring back to
Further, as shown, a parity bit 30 value is computed for each row, and therefore three parity bits 30 are appended at the end of each set of data bits. Note that a single parity bit 30 is in fact a 1-bit CRC code with the generator polynomial X+1. In other words, three CRC bits can be used for different equal-size classes (Class 1, Class 2 and Class 3 in
It should be noted that the present system as illustrated and described herein is not intended to identify and correct all bit errors, but rather to decrease the number of bit errors. Additionally, it should be noted that the specific percentages for the dominant error events as shown in
Referring again to the embodiment illustrated in
The detection algorithm 12 decodes the incoming signal waveform through continually computing the accumulated metrics and branch metrics at each time step. At the end of each period of decoded P bits, the accumulated metrics are updated if the error detection mechanism checks. In other words, the detection algorithm 12 makes a decision on previous bits (by choosing a path that passes the EDC decoding) and employs an update step before proceeding to the next decoding period of P bits. As the trellis 38 evolves in time, the detection algorithm 12 eliminates half of the possible paths, i.e. the false paths, in the trellis 38 at each time step. At the end of each P-bits period, a decision is made and an update step is executed on the accumulated metrics before proceeding to the decoding of the next chunk. The reason for such a periodic update is to increase the probability of correcting an error event (if there is any) before the trellis 38 evolves more and the detection algorithm 12 eliminates more false paths. This suggests that for a fixed N, if P is large, we expect less error corrections. On the contrary, one can choose P small to increase the probability of correcting a majority of the error events at the output of the NPMLD. However, having smaller P implies more frequent periodic updates meaning that more redundant bits are used for error detection. Thus, the proposed detection algorithm 12 offers a tradeoff, i.e., an improved performance is possible at the expense of a decreased user density.
Additionally, illustrated at the top of
Further, as shown, each data chunk 36 is evaluated, with error events thus being detected, through the operation of a separate error detection code (EDC). Each EDC for each data chunk 36 can be equated with and/or represented by the update stage 32 illustrated in
The detection algorithm 12 and/or the update stage 32 of the detection algorithm 12 is based on the trellis 38, with the trellis 38 encompassing a plurality of nodes 40. Additionally, as illustrated in
As described herein, the number of most probable sequences (N) identified can be varied. Generally speaking, the detection algorithm 12 is able to achieve a better performance with a larger number of most probable sequences (a larger N), but there is a corresponding tradeoff related to an increase in complexity and redundancies that is necessary when utilizing a greater number of most probable sequences.
Once the path metrics 42 have been computed for each node of the trellis 38, the update stage 32 next illustrates a C value selector 44 in which the first q smallest path metrics 42 are chosen out of all 2KN possible paths from the List-Viterbi detection algorithm 12. The set of the first q smallest path metrics 42 as chosen via the operation of the Q value selector 44 is illustrated as Cq={Cm1, Cm2, . . . , Cmq}, with each chosen path metric 42 being associated with a corresponding associated bitstream 46. Additionally, as illustrated, each associated bitstream 46 includes EDC bits for purposes of decoding.
It should be noted that number of path metrics 42 chosen by the Q value selector 44 can be any number of candidates from all of the nodes 40 on the trellis 38, with a higher number generally leading to better performance, but also requiring greater complexity and redundancies for the detection algorithm 12 of the error correction system 10. For example, in different embodiments, the number of path metrics 42 chosen by the Q value selector 44 can be two, four, six, eight, ten, twelve, fourteen, or any other number.
The reason for utilizing the Q value selector 44 is to minimize false EDC checks caused by less probable sequence candidates (i.e. candidates with large accumulated metrics). Especially when P and N are large, the detection code is expected to see more false EDC checks. By choosing an appropriate q value with the Q value selector 44, the EDC is inhibited from checking false paths that potentially have more error events than the maximum likelihood path that fails the EDC decoding.
After selecting the smallest q accumulated path metrics 42 via operation of the value selector 44, based on the associated decoded bitstreams of q paths, an error detector 48 evaluates each associated bitstream 46 using EDC decoding. In
Finally, the accumulated path, metrics are updated with a metric updater 50 to provide updated path metrics 52. In this example, via the metric updater 50, the accumulated metrics of all the paths except the second and qth paths, i.e. the paths that flagged 0s or “failed”, are discarded i.e., set to ∞ (or other typically large value). Additionally, the accumulated metrics that do not belong to Cq are also set to ∞. The updated path metrics 52 are then fed back into the update stage 32 as related to each node 40 on the trellis 38, and the process is repeated. Further, it should be noted that for those paths that failed, the next most probable sequence for that particular node 40 is chosen for the next pass through the update stage 32. For example, if the C1,1 path metric for the first node of the trellis 38 failed for the first pass through the update stage 32, on the next pass through the update stage 32, the C1,2 path metric for the first node of the trellis 38 would be utilized and/or evaluated.
In contrast to the passes through the update stage 32 that find one or more checks, as discussed above, it is possible that there is “no check” i.e., EDC indicates that none of the paths is correct. Since the detection algorithm 12 is expected to continue decoding, a decision should be made about which path is to be chosen. There are more than one type of decision as mentioned below. Additionally, the accumulated metrics are not updated if there is “no check”.
Type 1:
One of the simplest choices is to choose the path with a minimum accumulated metric. In other words, at each periodic update step, if the EDC indicates no path is reliable, the detection algorithm 12 decides that the correct path is the one with the smallest accumulated metric.
Type 2:
As previously noted, during application, the EDC flags either 0 or 1. Thus, if no path checks the EDC, every path flags a 0. However, the EDC might have the capability of flagging some number 0≦a≦1 based on the number of errors associated with the path (message) to which this EDC is appended. In other words, for example, low value of ‘a’ could mean more number of bit errors. In that case, if there is no path with a flag 1, the detection algorithm 12 might choose the path with the largest ‘a’.
It should be noted that the decision process is updated as each data chunk 6 is evaluated via the corresponding EDC, i.e. via the update stage 32. Accordingly, the results improve as they are updated by going through each of the data chunks 36, and by the time the Mth data chunk 36 is evaluated, the results should be relatively good or near perfect.
Initially,
For a Lorentzian channel, the first order position jitter model is considered. Electronics and stationary transition noise samples are added to the signal waveform at the input of a low pass filter (LPF). Additionally, the signal-to-noise ratio (SNR) is computed at the input of the LPF and given by 2/(N0+Nm) where N0/2 and Nm/2 are the two sided spectral densities of two white Gaussian noise sources. Further, the ratio of the transition noise power to the total noise power is approximated by β=Nm/(N0+Nm). Perfect timing recovery and a 5th Butterworth LPF with a 3-dB cut-off at the Nyquist frequency is also assumed. PR4 equalizer is based on the minimum mean square error criterion and length of the filter is as long as the channel impulse response. Whitening filter coefficients are selected using linear prediction in Least Mean Squares (LMS) sense based on the current noise samples wn.
As provided herein,
Finally, as provided herein, the following tables present the practical performance results of the application of the proposed detection algorithm 12 using LTO waveforms in Table I, Table II and Table ill for chunk sizes of P=200 bits, P=1,000 bits and P=2,000 bits, respectively. Initially, each table shows the number and types of error events (such as shown in
As can be seen, the performance of the List-NPMLD detection algorithm utilizing any N is significantly better than the performance seen when simply utilizing the NPMLD detection algorithm. Moreover, as demonstrated in the tables, the performance of the List-NPMLD detection algorithm improves with increasing N, although such improvement is achieved at the expense of an increase in complexity and redundancies. For example, at P=200 bits, approximately 85% and 92% of the error events can be reduced using N=2 and N=3, respectively, as compared to the use of the NPMLD detection algorithm. Another way of looking at these results is to see the performance tradeoff between parameters N and P. For example, it can be observed that the proposed scheme with N=2 and P=200 bits gives almost the same performance compared to the system using N=5 and P=1,000 bits. However, the N=2 and P=200 setting requires almost 5 times the number of redundant bits for EDC, but only almost 40% circuit complexity as compared to those for the N=5 and P=1,000 setting.
Another observation that can be seen from these tables is that the distributions of these dominant error events (i.e. the percentages of the different types of error events) are roughly the same whether a List-NPMLD or a conventional NPMLD is used. This tends to suggest the idea that the proposed scheme may be effectively combined with some of the existing post processing methodologies. Such a combined design would be implemented in two steps: (Step 1) the List-NPMLD detection algorithm reduces the total number of error events without changing the distributions of error events, and (Step 2) an existing post processor focuses on the first one or two dominant error events and attempts to correct them. In this way, the combined post processor can improve performance even further.
As can, be seen, the proposed detection algorithm 12 and error correction system 10 achieve the reported performance gains by utilizing error detection codes 14 (illustrated in
As noted above, traditional post processors are suboptimum solutions and are usually not robust because they attempt to correct dominant error events at the expense of adding other unwanted errors (i.e. miss-correction). However, the proposed error correction system 10 has little chance of miss-correction because it always confirms the corrected sequence with EDC. Therefore, any potential miss-correction is inhibited as long as EDC functions properly.
The distributions of error events are functions of several parameters such as current recording density and the physical conditions of the read/write heads. As such parameters might change in time, the distributions of error events at the output of the NPMLDs may also change. Therefore, traditional approaches need to adaptively optimize the system parameters to obtain the reported performance gains. However, the proposed invention does not make any assumptions on the error event distribution and attempts to correct those error events without distinguishing one from the other. Therefore, the performance gain demonstrated herein can be effectively realized at any error event distributions.
While a number of exemplary aspects and embodiments of an error correction system 10 and a detection algorithm 12 (and related methods) have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and sub-combinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions and sub-combinations as are within their true spirit and scope.
