Patent Application
20070300104
In this embodiment, a memory controller, 202, drives differential signals along HSS link, 210, to a bit error rate reduction buffer, 208. When the differential signals reach the bit error rate reduction buffer, 208, the bit error rate reduction buffer, 208, may retrieve the clock and data, may buffer the data, may check for errors, and may reduce skew between lanes. In addition, the bit error rate reduction buffer, 208, may operate internally either in a serial or parallel mode. After data has been operated on by the bit error rate reduction buffer 208, it is resent serially along HSS link 212 to DIMM (Dual In-Line Memory Module), 204 and along HSS link 218 to DIMM, 206.
DIMM 204 includes an AMB (advanced memory buffer) 222. The AMB, 222, provides control and interface signals to the DRAMs (dynamic random access memory), 224, 226, 228; and 230, on the DIMM 204. DIMM 206 includes an AMB (advanced memory buffer) 232. The AMB, 232, provides control and interface signals to the DRAMs (dynamic random access memory), 234, 236, 238, and 240, on the DIMM 206.
Data may also be driven from DIMM 206 through HSS link, 220, through HSS link, 216, to the bit error rate reduction buffer, 208. In this block diagram, data is driven to the left. When the differential signals reach the bit error rate reduction buffer, 208, the bit error rate reduction buffer, 208, may retrieve the clock and data, may buffer the data, may check for errors, and may reduce skew between lanes. In addition, the bit error rate reduction buffer, 208, may operate internally either in a serial or parallel mode. After data has been operated on by the bit error rate reduction buffer 208, it is resent serially along HSS link 214 to memory controller 202.
Data may also be driven from DIMM 204 through RSS link, 216, to the bit error rate reduction buffer, 208. In this block diagram, data is driven to the left. When the differential signals reach the bit error rate reduction buffer, 208, the bit error rate reduction buffer, 208, may retrieve the clock and data, may buffer the data, may check for errors, and may reduce skew between lanes. In addition, the bit error rate reduction buffer, 208, may operate internally either in a serial or parallel mode. After data has been operated on by the bit error rate reduction buffer 208, it is resent serially along HSS link 214 to memory controller 202.
A HSS link, 468, drives the differential bit pair inputs, 415, of data recovery circuit, 408. Data and clock are retrieved from the HSS link, 468. The data recovery circuit, 408, through differential bit pair outputs, 417, 419, 421, and 423, drives lanes, 440, 442, 444, and 446, respectively, into the differential bit pair inputs, 425, 427, 429, and 431, of FIFOs, 424, 426, 428, and 430 respectively. A PLL may be used as part of the data recovery circuit, 408. Because data from FIFOs 424, 426, 428, and 430 is clocked out at nearly the same time, skew between lanes 456, 458, 460, and 462 may be reduced. Data from the outputs, 433, 435, 437, and 439, of FIFOs, 424, 426, 428, and 430 respectively is clocked in parallel through lanes, 456, 458, 460, and 462 into inputs, 441, 443, 445, and 447 of synchronizer 414. The parallel output, 449, of synchronizer 414 then synchronizes the data from lanes 456, 458, 460, and 462. The parallel out, 449, of synchronizer, 414, is then driven into serializer, 410, through bus 474. Serializer, 410, through differential bit pair outputs, 453, then drives HSS link 470. In this example, the HSS links pointing to the right, 464, and 466, have the same number of lanes. In this example, the HSS links pointing to the left, 468 and 470, have the same number of lanes. However, the HSS links that point to the right, 464 and 466 are not required to have the same number of lanes as the HSS links that point to the left, 468 and 470. HSS link 464 is not required to have the same number of lanes as HSS link 466. HSS link 468 is not required to have the same number of lanes as HSS link 470. Differential signals are not required for signals internal to the bit error rate reduction buffer, 402.
A HSS link, 556, drives the differential bit pair inputs, 596, of the data recovery circuit, 508. Data and clock are retrieved from the HSS link, 556. A PLL may be used as part of the data recovery circuit, 508. The differential bit pair outputs, 598, 500, 501, and 503 of the data recovery circuit, 508, drive lanes, 536, 538, 540, and 542, into the differential bit pair inputs, 505, 507, 509, and 511 of CRC (cyclic redundancy check) circuit, 514. If an error is detected, the fault-isolation indicator, 516, sends a signal that indicates an error may have occurred in lane 536, 538, 540, or 542. CRC circuit, 514, through differential bit pair outputs, 513, 515, 517, and 519, drives the differential bit pair inputs, 521, 523, 525, and 527, of serializer, 510 through lanes 544, 546, 548, and 550 respectively. Serializer 510 then sends the data through differential bit pair output, 529 to HSS link, 558. In this example, the HSS links pointing to the right, 552, and 554, have the same number of lanes. In this example, the HSS links pointing to the left, 556 and 558, have the same number of lanes. However, the HSS links that point to the right, 552 and 554 are not required to have the same number of lanes as the HSS links that point to the left, 556 and 558. HSS link 552 is not required to have the same number of lanes as HSS link 554. HSS link 556 is not required to have the same number of lanes as HSS link 558. Differential signals are not required for signals internal to the bit error rate reduction buffer, 502.
A HSS link, 614, drives the differential bit pair inputs, 682, of the data recovery circuit, 611. A PLL may be used as part of the data recovery circuit, 611. Data and clock are retrieved from the HSS link, 614. The differential bit pair outputs, 683, 684, 685, and 686 of the data recovery circuit, 611, drive lanes, 640, 641, 642, and 643, into the differential bit pair inputs, 695, 696, 697, and 698 of FIFOs, 609, 621A, 622A, and 623A, respectively. Because data from FIFOs 609, 621A, 622A, and 623A, is clocked out at nearly the same time, skew between lanes 636, 637, 638, and 639 may be reduced. Data from the outputs, 699, 600A, 601A, and 602A, of FIFOs, 609, 621A, 622A, and 623A respectively is clocked in parallel through lanes, 636, 637, 638, and 639 into inputs, 603A, 604A, 605A, and 606A of synchronizer 608. The parallel output, 610A, of synchronizer 608 then synchronizes the data from lanes 636, 637, 638, and 639. The parallel output, 610A, of synchronizer, 608, is then driven into the parallel input, 688, of CRC circuit, 610, though bus 632. If an error is detected, the fault-isolation indicator, 617A, sends a signal that indicates an error may have occurred in lane 636, 637, 638, or 639. CRC circuit, 610, through parallel output, 692, drives parallel input, 614A, of serializer, 607, through bus 644. Serializer, 607, through differential bit pair outputs, 615A, then drives HSS link 615. In this example, the HSS links pointing to the left, 614 and 615, have the same number of lanes. However, the HSS links that point to the right, 612 and 613 are not required to have the same number of lanes as the HSS links that point to the left, 614 and 615. HSS link 612 is not required to have the same number of lanes as HSS link 613. HSS link 614 is not required to have the same number of lanes as HSS link 615. Differential signals are not required for signals internal to the bit error rate reduction buffer, 600.
When the BER of an HSS link fails to meet a required specification, a bit error rate reduction buffer may be used to reduce the BER and meet the required specification. One way this may be accomplished is by physically dividing the HSS link into two separate HSS links, each link being about half the length of the original HSS link, and then physically and electrically connecting a bit error rate reduction buffer between the two divided HSS links. The bit error rate reduction buffer improves the BER by recovering data at a point with a higher signal-to-noise ratio. In addition, the bit error rate reduction buffer may indicate when an error occurs through a fault-isolation indicator.
The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The exemplary embodiments were chosen and described in order to best explain the applicable principles and their practical application to thereby enable others skilled in the art to best utilize various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments except insofar as limited by the prior art.
