The present invention relates to a method and a device for bit recovery in an asymmetric data channel, and to an apparatus for reading from and/or writing to recording media using such method or device.
In current harddisk and optical disk applications partial response maximum likelihood detectors (PRML, Viterbi) are used for recovering the data from a channel data stream.
Usually a digitised optical channel data stream is resynchronized to the channel clock using a phase locked loop (PLL) and a sample rate converter (SRC), then equalized with a filter setting representing the inverse channel behaviour and finally detected using a simple slicer and a bit detector.
An adaptive approach using a maximum likelihood decoder calculates the difference of the recovered data to the equalized data, e.g. with the least mean square (LMS) method, and uses this as adjusting information in order to get a coefficient set for the equalizer, which better fits to the channel characteristic. The LMS updating is typically implemented as follows:
Coeffnew=Coeffold+μ×ε(filtered vitout,eqout)×channel data
However, some approaches only consider the direction (+ or −) of the error signal ε.
It has been found that the cause of signal asymmetry shows different behaviour during a transition from one storage state (e.g. land) to another storage state (e.g. pit). By separately compensating both transition defects a better signal data representation is found for decoding the contained data bits using a maximum likelihood approach.
It is an object of the invention to improve the methods known from prior art.
According to the invention, a method for bit recovery in an asymmetric data channel comprises the steps of:
The invention combines the usage of a non-linear equalization filter with means for compensating both transitions separately. Adopting the separate adaptation processes to a non-linear equalization approach greatly improves the data detection using maximum likelihood decoders.
Favourably, the equalizer scheme is implemented at least twice in parallel. In this way it supports faster channel data streams. Alternatively, it is designed as a single circuit recalculating the new sample by working on different phases of a system clock.
According to a first implementation of the inventive solution, the system clock is faster than twice the channel clock. In this case the two coefficient sets may be switched over. According to a second implementation, the system clock is slower than twice the channel clock. In this case the switching is accomplished on different system clock phases.
Usually the modulation of a channel data stream is subject to certain runlength restrictions. This allows to use a slower system clock, since some calculations are no longer required.
The method or the device are advantageously used in an apparatus for reading from and or writing to optical recording media. However, they can be applied to any other signal detection means dealing with asymmetric signal distortions.
For a better understanding of the invention, an exemplary embodiment is specified in the following description with reference to the figures. It is understood that the invention is not limited to this exemplary embodiment and that specified features can also expediently be combined and/or modified without departing from the scope of the present invention. In the figures:
In
yk=h0+h1(x(k))+h2(x(k),x(k)) (1)
The known approach using an FIR filter only considers the term h1(x(k)). The polyphase term h2, which is basically a quadrature of the incoming signal, requires an additional DC compensation, which is taken into account by the factor h0.
Number | Date | Country | Kind |
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03012954 | Jun 2003 | EP | regional |
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Number | Date | Country | |
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20040247026 A1 | Dec 2004 | US |