The invention will be described in more detail with reference to the accompanying drawings, in which:
FIG. 1 is a circuit diagram of known detection means;
FIG. 2 is a set of signal diagrams I-V, for explaining the known detection means;
FIG. 3 (a-d) shows a record carrier (disk);
FIG. 4 shows bi-phase wobble modulation;
FIG. 5 is a circuit diagram of an embodiment of detection means according to the invention;
FIG. 6 is a table for further explaining the invention;
FIG. 7 is a circuit diagram of a further embodiment of the detection means according to the invention; and
FIG. 8 is a table for further explaining the further embodiment of the invention.
In these Figures parts or elements having like functions or purposes bear the same reference symbols.
FIG. 3
a shows a disk-shaped record carrier 1 which comprises a continuous track 9 intended for recording, which track is arranged in a spiraling pattern of turns 3. The turns may also be arranged concentrically instead of spiraling. The track 9 on the record carrier is indicated by a servo track in which, for example, a pregroove 4 enables a read/write head to follow the track 9 during scanning. A servo track may also be formed, for example, by regularly distributed sub-tracks which, in the servo track system, periodically cause signals to occur. FIG. 3b shows a cross-section taken on a line b-b of the record carrier 1, in which a transparent substrate 5 is covered by a recording layer 6 and a protective layer 7. The pregroove 4 may also be arranged as a land or be a material property that differs from its environment. The recording layer 6 may be deposited in an optical, magneto-optical, or magnetic manner by an apparatus for reading and/or writing information such as the known CD recordable or hard disk for computer use. FIGS. 3c and 3d show two examples of a periodic modulation (wobble) of the pregroove. This wobble causes an additional signal to arise in a servo track recorder. A comprehensive description of the CD system comprising disk information can be found in U.S. Pat. No. 4,901,300 and U.S. Pat. No. 5,187,699.
FIG. 4 shows bi-phase wobble modulation. An upper trace shows the wobble modulation for a word sync pattern, a second and third trace show the wobble modulations for data bits (one out of Data Bits 1 to 51). Predetermined phase patterns are used for indicating a synchronizing symbol (ADIP (ADdress In Pregroove) bit sync) and a synchronization of the full address word (ADIP word sync), and for the respective data bits (ADIP Data=‘0’, and ADIP data=‘1’). The ADIP bit sync is indicated by a single inverted wobble (wobble # 0). The ADIP word sync is indicated by three inverted wobbles immediately following the ADIP bit sync, whereas data bits have non-inverted wobbles in this area (wobble # 1 to 3). An ADIP Data area comprises a number of wobble periods assigned to represent one data bit, in FIG. 4 the wobble periods are numbered 4 to 7 (=wobble # 4 to 7). The wobble phase in the first half of the ADIP Data area is inverse to the wobble phase in the second half of the area. As such each bit is represented by two sub-areas having different phases of the wobble, i.e. called bi-phase. Data bits are modulated as follows: ADIP Data=‘0’ is represented by 2 non-inverted wobbles followed by two inverted wobbles, and ADIP data=‘1’ by the opposite. In this example the modulation for data bits is fully symmetrical, giving equal error probabilities for both data bit values. However, other combinations of wobbles and inverted wobbles, or other phase values may be used. Monotonic wobbles may be used after the first data bit, or further data bits may be encoded thereafter. Usually a large majority of the wobbles is not modulated (i.e. has the nominal phase) for ensuring an easy lock and a stable output of a PLL. In this example the 8 possibly modulated wobbles are followed by 85 non-modulated (i.e. monotonic) wobbles (wobble # 8 to 92). The output frequency of the PLL has to be as stable as possible, because during writing the write clock is derived from the PLL output.
An ADIP word comprises 52 bits, which corresponds to 52*93 wobbles, and 1 wobble=32 channel bits. For the DVD format a channel code EFM+ is used, and channel bits are clustered in EFM sync frames of 1488 channel bits. Hence one ADIP bit corresponds to 2 EFM sync frames, and the ADIP word corresponds to 4 sectors in the DVD format. An ECC (Error Correction Code) block in the DVD format comprises 16 sectors, hence an ECC block corresponds to 4 ADIP words. So one ADIP Word Sync is used every fourth sector to indicate the start of a new address (i.e. a new full ADIP word).
Briefly stated, the detection of the ADIP words is done in a number of steps:
- STEP 1: Lock on to the wobble (with the aid of a PLL).
- STEP 2: Detect the position of the bitsync or, in other words, detect the position of the ADIP unit.
- STEP 3: Lock on to the bitsync and use a “flywheel” to stay in lock even if a bitsync is missed.
- STEP 4: Detect the SYNC.
- STEP 5: Lock on to the SYNC and use a “flywheel” to stay in lock even if a wordsync is missed.
- STEP 6: Detect data bits ZERO or ONE.
- STEP 7: Use ECC to correct errors and extract the correct addresses.
The invention is mainly focused on STEPS 2, 3, 4, 5, and 6.
FIG. 5 shows a circuit diagram of an embodiment of detection means according to the invention. The circuit as shown in FIG. 1 also belongs to this embodiment, except for the comparator CMP. The detection means further comprises a chain CHDL of signal time delay elements, an input of the chain CHDL being coupled to receive the further signal fs; and combining means CBMNS having combining inputs coupled to signal taps of the chain CHDL, such that the number of the combining inputs and the positions of coupling the combining inputs to the signal taps of the chain CHDL correspond to the information in the signal s. In this example the information comprises a bit synchronization part followed by a word synchronization part which will be further denoted SYNC, and possible data ZERO and data ONE types of data bit parts. The combining means CBMNS delivers a combining output signal “zero” corresponding to data ZERO, a combining output signal “one” corresponding to data ONE, and a combining output signal “sync” corresponding to SYNC.
The detection means further comprises processing means PRMNS for processing the combining output signals “zero”, “one” and “sync”. The processing is accomplished such that during a predetermined number of time intervals Ti (see FIG. 2), in each time interval Ti the lowest (highest) signal value of the signal values of the combining output signals “zero”, “one” and “sync” is detected together with an accompanying position number corresponding to the corresponding time interval Ti. The position number corresponding to the lowest (highest) detected signal value within the predetermined number of time intervals Ti is deemed to be the correct position P0 of the SYNC. As is shown in the Table of FIG. 6, for every wobble (wobble 0 to wobble 92) the minimum value of a ZERO, ONE, or SYNC is determined and retained with the corresponding position number. In this example the minimum detected value is −32. This means that SYNC detection occurs where the deemed correct position P0 is 17. The pattern belonging to this 17th wobble is indicated as the “Minimum pattern” in FIG. 5. In this patent application, by way of example, the detection means is defined such that a determination of a minimum value (see FIG. 6) and the associated “Minimum pattern” which corresponds to the “best pattern matching principle” is carried out. It is also possible, however, to define the detection means such that a maximum value and the associated “Maximum pattern” are determined. The “Maximum pattern” then corresponds to the “best pattern matching principle”.
FIG. 7 shows a circuit diagram of a further embodiment of the detection means according to the invention in which the detection means further comprises further processing means FPRMNS for further processing the deemed correct positions P0 delivered by the processing means PRMNS. This further embodiment deals with STEPS 3-6. The further processing means FPRMNS examines the positions of the deemed correct positions P0 of the SYNC during a substantially longer period of time as compared with the predetermined number of time intervals Ti. The further processing means FPRMNS is now further explained in conjunction with the Table of FIG. 8 in which the “flywheel principle” is illustrated.
The further processing means FPRMNS comprises an up/down counter CNT having a registered value RCN which is incremented (decremented) by a unit value up to a predetermined reference value PRV of the up/down counter CNT, whenever a deemed correct position P0 of the SYNC occurs at the position expected by the further processing means FPRMNS. In this example the predetermined reference value PRV is equal to 4. The registered value RCN is decremented (incremented) by a unit value whenever a deemed correct position P0 of the SYNC does not occur at the position expected by the further processing means FPRMNS. The higher the registered value RCN, the higher the “confidence” that the positions P1 delivered by the further processing means FPRMNS are correct. The further processing means FPRMNS which delivers positions P1 of the SYNC with improved position reliability is accomplished by the manner of operation of the further processing means FPRMNS in which the position P1 of the SYNC is equal to the position expected by the further processing means FPRMNS as long as the registered value RCN is above (below) a further predetermined reference value FPRV, while the position P1 of the SYNC is equal to the position P0 delivered by the processing means PRMNS when the registered value RCN becomes equal to the further predetermined reference value FPRV, in which latter case the up/down counter CNT is reset. In this example the further predetermined reference value FPRV is equal to zero. In FIG. 7 there are in fact two “flywheels” indicated: a BS (Bitsync) and a WS (wordsync) “flywheel”. Both have similar operation. Therefore, the operation of only one “flywheel” is shown in FIG. 8.
Consider the table of FIG. 8. The first (upper) row contains positions PRMNS=16, FPRMNS=16, and RCN=4. RCN=4 means there is a high “confidence” that P1 is a correct position. As long as RCN is above zero, the position delivered by the further processing means FPRMNS is kept constant, even if the position P0 is changed, which occurs for the first time in the 4th row (P0=30), the only effect being a lowering of the registered value RCN by one unit (in this case from 4 to 3). In the 10th row RCN becomes 0. The effect is that the up/down counter CNT is reset and P1 assumes a new value delivered by P0. Then the procedure is repeated.
It is to be emphasized that the detection means are not limited to the examples disclosed in this patent application. The detection method may also be applied, for example, to Blu ray disks (formerly denoted DVR) in which MSK (Minimum Shift Keying) is applied. MSK is well known from the literature. Briefly summarized, in MSK a bitsync is spread over 3 wobbles: one wobble period having a cosinewave with 1.5 times the monotonic wobble frequency, a wobble period one time the monotonic wobble frequency, and a wobble period with 1.5 times the monotonic wobble frequency.
Alternative modulation forms may also be used.
Patent Application
20080037394
