1. Field of the Invention
The present invention relates generally to electronic device testing, and more particularly, to synchronization techniques used in testing integrated circuit (IC) devices that output high-speed serial data streams.
2. Description of the Related Art
Next generation microprocessors will use a large number of high-speed serial links to communicate with external memory and I/O devices. In order to obtain accurate test results of such microprocessors, it is important that the continuous stream of bits (0's and 1's) output by them is consistently strobed near the center of the bit and away from the transitions between the bits. If the strobes are positioned near the bit transitions, inaccurate strobe readings, e.g., 0 strobed as a 1 or 1 strobed as a 0, might result and cause inaccurate test results.
A conventional automated test equipment (ATE) uses a binary search method to locate the center of the bit. The binary search method is carried out during the initialization phase of testing when the device under test is outputting an alternating stream of 0's and 1's. With this method, two strobe points separated by the bit interval are initially selected. Then, a third strobe point that is halfway between the initial two strobe points is selected. The reading from the third strobe point is compared with the readings from the first two, and the pair that exhibits a transition (0 to 1 or 1 to 0) is selected as end points of a fourth strobe point that is halfway between the pair. The reading from the fourth strobe point is compared with the readings from the end points, and the pair that exhibits a transition (0 to 1 or 1 to 0) is selected as end points of a fifth strobe point that is halfway between the pair. This process is repeated until the bit transition is identified with a predetermined degree of accuracy. The bit strobe position is then computed as the position of the bit transition plus one-half of the bit interval.
The binary search method used in the conventional ATE, as described above, is too slow and cannot be used while a test is ongoing. As a result, they are unable to correct for bit misalignments that may result during testing, e.g., during clock starts and stops, and from drifts caused by heating up or cooling down of the device.
The invention is directed to a bit synchronization method, and an apparatus implementing such a method, for adjusting the timing of the strobe during initialization and testing so that the data bit stream being analyzed is consistently strobed near the center of the bit.
The invention implements bit synchronization techniques that employ a programmable device, such as a field programmable gate array (FPGA). The programmable device selects from a number of different time sets that are used to strobe the data bit stream. Each of the different time sets positions the strobe at a unique reference strobe position along a single bit interval. The programmable device evaluates the strobe readings generated using the different time sets and selects one of the time sets as the one to be used for subsequent strobing of the data bit streams.
More specifically, for each time set, the programmable device records the number of zeroes that are read from a predefined data bit stream of alternating 0's and 1's within a set time period. The time set that generates the most number of zeroes is selected as the one to be used for subsequent strobing of the data bit streams. If multiple time sets generate the most number of zeroes, the time set that is at or near the center of the largest contiguous block of such time sets is selected as the one to be used for subsequent strobing of the data bit streams.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
In the preferred embodiment, the digital instrument 130-1 includes a bus interface field programmable gate array (FPGA) 210, a pair of FPGAs 220, 230 and their associated dual inline memory modules (DIMMs) 225, 235, eight timing generation circuits 240 (only one of which is illustrated), and eight pin electronics circuits 250 (only one of which is illustrated). Each of the timing generation circuits 240 is connected to a different one of the pin electronics circuits 250, and each of the eight pin electronic circuits 250 is connected to a different digital pin of the DUT 190 through the fixture 140. There are two sets of eight data lines between the timing generation circuits 240 and the FPGAs 220, 230. The first set connects each of the eight timing generation circuits 240 to the FPGA 220 and the second set connects each of the eight timing generation circuits 240 to the FPGA 230. The FPGAs 220, 230 are also connected to their respective DIMMs 225, 235, and to the bus interface FPGA 210, which interfaces with the system bus 205.
The components of the digital instrument 130-1, shown in
The digital instrument 130-1 strobes response signals from the output digital pins of the DUT 190 to generate a continuous stream of data bits that are to be compared (16 bits or 1 word at a time) against an expect data packet that is retrieved from the DIMM 235. The digital instrument 130-1 performs this test continuously, and issues a fail trigger each time there is a mismatch.
The timing generation circuits 240 store in memory a number of different time sets (or strobe markers) that they use to strobe the data streams from the digital pins of the DUT 190. The FPGA 230 selects a time set for each pin, in accordance with the bit synchronization method that is described below, and communicates its selections to the timing generation circuits 240 through the FPGA 220. When the timing generation circuits 240 receive the selections made by the FPGA 230, they retrieve the selected time sets from memory and strobe the data streams from the digital pins of the DUT 190 using the selected time sets.
Each time set stored in memory of the timing generation circuits 240 is offset from an adjacent time set by a fraction of the bit interval. In the embodiment of the invention described herein, 16 different time sets (Ts0, Ts1, . . . , Ts15) are stored in memory. If the bit rate of the data stream output by the DUT 190 is 2.5 Gigabits/second, the time interval between the time sets is 25 picoseconds. The following table illustrates the different time sets that are stored in memory. Each timing value stored in the table is defined in picoseconds relative to a system reference clock that is synchronized to the master clock 136.
Before the strobed data stream of words is compared with expect data packets, it is necessary to align the data stream of words to the expect data packets. This process is known in the art as frame synchronization or frame alignment. This process needs to be separately performed because the digital instrument 130-1 begins generating the data stream of words from the response signals (a continuous stream of 0's and 1's) without regard to when the response signals that are to be converted and compared with the expect data packets begin arriving from the output digital pins of the DUT 190.
The FPGA 230 includes a bit synchronization module 305 for performing bit synchronization or eye centering, a frame synchronization module 310 for performing frame synchronization or frame alignment, a unit interval (UI) counter 320 that is incremented each time a word is received by the FPGA 230, a message block interface 330 for communicating with the FPGA 220, a synchronization detector 335 for detecting a synchronization code in the data stream, an idle detector 340 for detecting an idle code in the data stream of words received from the timing generation circuit 240, a high-speed buffer queue 350 for delaying the data stream of words prior to comparing them with an expect data packet, a comparator 360 for performing the comparison, and an address memory 370 that stores in a sequential manner the memory locations of expect data packets to be retrieved from the DIMM 235. The sequence of expect data packets to be retrieved from the DIMM 235 is specified by the test program.
The bit synchronization module 305 receives the strobed data stream of words from the timing generation circuit 240. During the initialization phase of testing and during testing when the synchronization detector 335 detects a synchronization code in the data stream, the bit synchronization module 305 is active. When it is active, the bit synchronization module 305 selects the time sets (Ts0, Ts1, Ts2, . . . , Ts15) in sequence, communicates the selection to the timing generation circuit 240 through the message block interface 330 and FPGA 220, and counts the number of zeroes appearing in the data stream for a set period of time. After all 16 time sets have been selected and the number of zeroes associated with each of the time sets counted in this manner, the bit synchronization module 305 selects one of the time sets as the time set to be used during subsequent testing. The selection process is described below with reference to
The frame synchronization module 310 is illustrated in further detail in
When the frame synchronization code is found, the UI counter 320 is initialized, and a frame synchronization detect message including a bit position corresponding to the start of a frame is sent to the message block interface 330. Frame synchronization is performed pin by pin. Therefore, each copy of the circuit shown in
After frame synchronization, the frame synchronization module 310 is not used, and the UI counter 320 is incremented each time a new word (corresponding to a set of 16-bits measured from the frame synchronized bit position) arrives from the corresponding timing generation circuit 240. Also, each time the UI counter 320 is incremented, the counter reading is communicated to the message block interface 330. The new word is also supplied to the idle detector 340 and stored in the high-speed buffer queue 350. The high-speed buffer queue 350 is configured as a first-in, first out (FIFO) buffer so that each time a new word arrives from the corresponding timing generation circuit 240, all of the words already in the buffer queue 350 advance one position away from the start position of the buffer towards the end position of the buffer, and the new word is stored in the start position of the buffer. When the arrival of the next new word causes the word stored at the end of the buffer to exit: (i) a pointer 375 associated with the address memory 370 is advanced once; (ii) an expect data packet is retrieved from the DIMM 235 at the memory location indicated by the pointer 375; and (iii) the comparator 360 performs a comparison of the exiting word against the retrieved data packet. If there is a mismatch, a fail trigger is issued to the message block interface 330.
A typical DUT may have one or two of its output digital pins designated as the pin(s) at which idle codes appear. If one pin is designated (e.g., Pin 0), the idle detector 340 associated with the stream of data packets corresponding to this pin is activated and looks for an idle code (e.g., ‘1111’) in each new word that it is supplied (e.g., in the 4 most significant bit positions). All other idle detectors are turned off. For example, an idle state will be determined in the following situation:
but not in the following situation:
If two pins are designated (e.g., Pin 0 and Pin 1), the two idle detectors 340 associated with the streams of data packets corresponding to the two pins are activated, and each of the two idle detectors 340 look for an idle code (e.g., ‘11’) in each new word that it is supplied (e.g., in the 2 most significant bit positions). All other idle detectors are turned off. If both idle detectors 340 find the idle code at the same time (or at the same counter reading), it is determined that the DUT 190 is under an idle state at that time. For example, an idle state will be determined in the following situation:
but not in the following situation:
When the idle state is determined, the UI counter reading associated with the word(s) in which the idle code was detected is stored in the message block interface 330. All words having the same UI counter reading are determined to be idle data packets and are not compared with expect data packets.
For example, assume there are two digital instruments, each connected to four output digital pins of the DUT 190. The streams of frame synchronized data packets generated from the response signals from these pins will be referred to as first through eighth streams. The first digital instrument processes the first through fourth streams, and the second digital instrument processes the fifth through eighth streams.
In the example, the first and second streams are examined for idle codes. When the idle code is detected in data packets in the first and second streams by the idle detectors 340, the counter reading of the UI counters 320 is stored at the message block interfaces 330 associated with the first and second streams and communicated to the message block interfaces 330 associated with the third and fourth streams internally through the FPGA 220, and communicated to the message block interfaces 330 associated with the fifth through eighth streams through the FPGA 220 of the first digital instrument, the bus interface FPGA 210 of the first digital instrument, the system bus 205, the bus interface FPGA 210 of the second digital instrument, and the FPGA 220 of the second digital instrument.
As the data packets in the third through eighth streams exit their corresponding high-speed buffer queues 350, the FPGA 230 examines the corresponding message block interface 330 to determine if the comparison of the exiting data packet should be suppressed. If the comparison is to be suppressed: (i) the expect data pointer 375 is not advanced; (ii) the expect data packet is not retrieved; and (iii) the comparator 360 does not compare the exiting data packet against any expect data packet. If the comparison is to be made: (i) the expect data pointer 375 is advanced once; (ii) the expect data packet is retrieved from the memory location of the DIMM 235 indicated by the expect data pointer 375; and (iii) the comparator 360 compares the exiting data packet against the retrieved expect data packet.
The determination of whether the comparison of the exiting data packet should be suppressed or performed is made with respect to the UI counter reading associated with the detection of an idle code, the size of the high-speed buffer queue 350, and the current UI counter reading. If the current UI counter reading is equal to the idle code UI counter reading+buffer size/16 bits, the comparison is to be suppressed. If not, the comparison is to be performed. In the preferred embodiment, the buffer size is 1024 bits. Therefore, an idle code that is detected at a particular point in time will affect the determination of whether the comparison of the exiting data packet should be suppressed or performed 64 counter increments after the particular point in time. If a new 16-bit word is processed every 5 nanoseconds, this means that the high-speed buffer queue 350 delays the comparison by 320 nanoseconds.
Referring to
Referring to
Special idle message codes may be used in situations where the DUT 190 is expected to be in an idle state for more than one time interval or UI counter increment. For example, an idle message code ‘1001’ may be used as an idle code ON/OFF toggle so that all UI counter readings between the ON toggle and the OFF toggle, inclusive, are considered to be UI counter readings corresponding to an idle state of the DUT 190. As a consequence, all data packets corresponding to these UI counter readings will be considered idle data packets and will not be used in the comparisons against expect data packets.
The 16 different reference strobe points span the width of the bit interval and have equal spacing between them. The spacing is equal to the bit interval divided by the number of different reference strobe points. In the embodiment described herein, the spacing is 25 picoseconds (=400 picoseconds/16). In the illustration, the reference strobe point associated with the time set Ts0 is shown to be at the beginning of the bit interval. However, this is not necessarily the case. In practice, the reference strobe point associated with the time set Ts0 may be at any point along the bit interval.
In Step 711, the next time set in sequence is selected by the FPGA 230. During the initial pass, the first time set Ts0 is selected. In Step 712, the timing generation circuit 240 strobes the data bit stream from the DUT 190 using the selected time set for 100 unit intervals (“UIs”; also referred to as bit intervals). The strobe rate is set to be equal to the bit rate of the DUT 190. Therefore, if the bit rate of the DUT 190 is 2.5 Gigabits/second, the data bit stream from the DUT 190 is strobed every 400 picoseconds.
In Step 713, the FPGA 230 records the number of zeroes in the data stream generated by the timing generation circuit 240 using the selected time set. Steps 711-713 are carried out for all 16 time sets. After the last time set (Step 714), the FPGA 230 identifies the time set that generated the most number of zeroes (Tsmax). If there are more than one Tsmax's (Step 715), the FPGA 230 identifies a largest contiguous block of Tsmax's (Step 716) and determines the time set that is at, or adjacent to, the center of this block as the time set to be used for subsequent strobing of the data (TsC) (Step 717). If there is only one Tsmax, the FPGA 230 determines Tsmax as the time set to be used for subsequent strobing of the data (Step 718).
Alternatively, if a contiguous block of Tsmax's appears at the beginning of the bit interval (e.g., Ts0, Ts1, Ts2, Ts3, Ts4) and at the end of the bit interval (e.g., Ts14, Ts15), the two contiguous blocks are combined into a single block (e.g., Ts14, Ts15, Ts0, Ts1, Ts2, Ts3, Ts4) and if this block is the largest of the contiguous blocks, the time set that is at, or adjacent to, the center of this block (e.g., Ts1) is selected as the time set to be used for subsequent strobing of the data.
During any one synchronization interval (20 UIs), only one time set is selected from sixteen time sets (Ts0, Ts1, Ts2, . . . , Ts15). The time set Ts0 is selected during the first synchronization interval. The time set Ts1 is selected during the second synchronization interval and so forth until all sixteen time sets are selected.
In Step 910, the synchronization detector 335 continually checks for the synchronization code. If the synchronization code is detected, the next time set in sequence is selected by the FPGA 230 (Step 911). During the initial pass, the first time set Ts0 is selected. In Step 912, the timing generation circuit 240 strobes the data bit stream from the DUT 190 using the selected time set for 20 UIs. The strobe rate is set to be equal to the bit rate of the DUT 190. Therefore, if the bit rate of the DUT 190 is 2.5 Gigabits/second, the data bit stream from the DUT 190 is strobed every 400 picoseconds.
In Step 913, the FPGA 230 records the number of zeroes in the data stream generated by the timing generation circuit 240 using the selected time set. Steps 910-913 are carried out for all 16 time sets. After the last time set (Step 914), the FPGA 230 identifies the time set that generated the most number of zeroes (Tsmax). If there are more than one Tsmax's (Step 915), the FPGA 230 identifies a largest contiguous block of Tsmax's (Step 916) and determines the time set that is at, or adjacent to, the center of this block as the time set to be used for subsequent strobing of the data (TsC) (Step 917). If there is only one Tsmax, the FPGA 230 determines Tsmax as the time set to be used for subsequent strobing of the data (Step 918).
Alternatively, if a contiguous block of Tsmax's appears at the beginning of the bit interval (e.g., Ts0, Ts1, Ts2, Ts3, Ts4) and at the end of the bit interval (e.g., Ts14, Ts15), the two contiguous blocks are combined into a single block (e.g., Ts14, Ts15, Ts0, Ts1, Ts2, Ts3, Ts4) and if this block is the largest of the contiguous blocks, the time set that is at, or adjacent to, the center of this block (e.g., Ts1) is selected as the time set to be used for subsequent strobing of the data.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
This application is a continuation-in-part of application Ser. No. 10/924,675, filed Aug. 24, 2004, entitled “Non-Deterministic Protocol Packet Testing.”
Number | Date | Country | |
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Parent | 10924675 | Aug 2004 | US |
Child | 10948709 | Sep 2004 | US |