BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates a PMOS transistor used in a CMOS circuit;
FIG. 2 illustrates a NMOS transistor used in a CMOS circuit;
FIG. 3 is a block diagram of a conventional adaptive body biasing circuit.
FIG. 4 is a block diagram of a body biasing control circuit according to an embodiment of the present invention;
FIG. 5 is a table showing exemplary body voltages which are generated by a control circuit according to indexes;
FIG. 6 is a block diagram of a body bias generator illustrated in FIG. 4;
FIG. 7 illustrates waveform diagrams of an enable signal and a macro block selection signal;
FIG. 8 illustrates switching configurations of demultiplexers, according to the logic states of the enable signal and the macro block selection signal; and
FIG. 9 is a circuit diagram of register trees illustrated in FIG. 6.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, like numbers refer to like elements throughout.
FIG. 4 is a block diagram of a body biasing control circuit 10 according to an embodiment of the present invention which includes a lookup table 41, a control unit 43, and a power management unit 45. Lookup table 41 records indexes which represent body voltages corresponding to operating states of macro block 100 and macro block 200. In particular, indexes VB(A) represent body voltages when macro block 100 and macro block 200 are in an active state and indexes VB(S) represent body voltages when macro block 100 and macro block 200 are in a standby state. Power management unit 45 reads the indexes VB corresponding to the operating states of macro blocks 100 and 200 from lookup table 41 and provides the indexes VB to control unit 43. Power management unit 45 also generates an enable signal ON and a macro block selection signal SEL for controlling control unit 43. Control unit 43 receives the corresponding indexes VB and generates body voltages PBODY and NBODY corresponding to the operating states of macro blocks 100 and 200 and supplies these voltages to the corresponding macro blocks. The body voltage PBODY is applied to PMOS transistors associated with the respective macro blocks 100 and 200 and the body voltage NBODY is applied to NMOS transistors of the respective macro blocks 100 and 200. Although FIG. 4 illustrates two (2) macro blocks 100 and 200 controlled by control unit 43, more macro blocks may be controlled by the same control unit 43 if necessary. Control unit 43 includes a decoder 431, a body bias generator 433, and an amplifier 435. Decoder 431 decodes an index VB received from power management unit 45 and supplies output bits ADR0-ADRn to body bias generator 433. In response to output bits ADR0-ADRn, body bias generator 433 generates body voltages suitable for the operating states of the respective macro blocks 100 and 200. Amplifier 435 receives and amplifies the voltages and supplies body voltages PBODY and NBODY to the corresponding macro blocks 100 and 200.
FIG. 5 is a table showing exemplary body voltages generated by control unit 43 according to indexes VB. Indexes VB(000)-VB(110) are associated with index VB(A) representing body voltages when macro blocks 100 and 200 are in an active state. Indexes VB(111) is an index VB(S) representing a body voltage when macro blocks 100 and 200 are in a standby state. The body voltages NBODY that are to be applied to the NMOS transistors and body voltages PBODY that are to be applied to the PMOS transistors correspond in pairs to each index VB. The number of bits of each index VB determines the accuracy of body biasing. That is, as the number of bits of each index increases, the body voltages NBODY and PBODY are more precisely controlled, but the body biasing control circuit becomes more complex. The indexes VB are determined after chip manufacture. By measuring an operating speed while changing index values in a unit of each macro block, selection of an index associated with a desired operating speed may be obtained.
In operation, power management unit 45 reads an index VB (for example, “000”) of a macro block that is to be controlled from lookup table 41. Decoder 431 decodes the index VB(000) and the output bits ADR0-ADRn of decoder 431 become “10000000”. Accordingly, a body voltage NBODY of 0.4V and a body voltage PBODY of 1.4V are generated by body bias generator 433 and amplifier 435. These voltages are supplied from amplifier 435 to macro block 100 or 200 in accordance with the logic states of the enable signal ON and the macro block selection signal SEL. For example, if the enable signal ON is a logic “1” and the macro block selection signal SEL is a logic “0”, body voltage NBODY (0.4 V) and body voltage PBODY (1.4 V) are supplied to macro block 100. If the enable signal ON is a logic “1” and the macro block selection signal SEL is a logic “1”, body voltage NBODY (0.4V) and the body voltage PBODY (1.4V) are supplied to macro block 200.
FIG. 6 is a block diagram of the body bias generator 433 illustrated in FIG. 4. Body bias generator 433 includes a plurality of register trees 61A and 61B, a plurality of level shifters 63A and 63B and a selection circuit 65. The register tree 61A and the level shifter 63A are associated with macro block 100 and register tree 61B and level shifter 63B are associated with macro block 200. In response to the enable signal ON and the macro block selection signal SEL, selection circuit 65 demultiplexes the output bits ADR0-ADRn of decoder 431 and outputs the results to level shifter 63A or 63B. The selection circuit 65 includes a plurality of demultiplexers 651-65n for demultiplexing the respective output bits ADR0-ADRn. Demultiplexers 651-65n are controlled by the enable signal ON and the macro block selection signal SEL. FIG. 7 illustrates exemplary waveform diagrams of the enable signal ON and the macro block selection signal SEL.
FIG. 8 illustrates switching configurations of demultiplexers 651-65n according to logic states of the enable signal ON and the macro block selection signal SEL. If the enable signal ON becomes a logic “0”, demultiplexers 651-65n are turned off and output bits ADR0-ADRn of decoder 431 are not supplied to level shifters 63A and 63B. If the enable signal ON is a logic “1” and the macro block selection signal SEL is a logic “0”, the output bits ADR0-ADRn of decoder 431 are output to level shifter 63A. If the enable signal ON is a logic “1” and the macro block selection signal SEL is a logic “1”, the output bits ADR0-ADRn of decoder 431 are output to level shifter 63B.
Referring back to FIG. 6, level shifters 63A and 63B convert voltage levels of output bits ADR0-ADRn to voltage levels which can control switches S31-S34 and S51-S54 illustrated in FIG. 9 associated with the corresponding register trees 61A and 61B, and outputs the converted voltage levels of output bits /ADR0-/ADRn. Level shifters 63A and 63B are also configured to supply output bits ADR0-ADRn. The voltage levels of the output bits ADR0-ADRn are converted using level shifters 63A and 63B because the voltage levels for controlling switches S31-S34 consisting of PMOS transistors are different from the voltage levels used for controlling switches S51-S54 consisting of NMOS transistors.
Register tree 61A generates body voltages suitable for the operating state of the corresponding macro block 100 in response to the output bits ADR0-ADRn and the converted output bits /ADR0-/ADRn. The body voltages generated by register tree 61A are amplified by amplifier 435 such that final body voltages PBODY1 and NBODY1 are supplied to macro block 100. Similarly, register tree 61B generates body voltages suitable for the operating state of the corresponding macro block 200 in response to the output bits ADR0-ADRn and the converted output bits /ADRO-/ADRn. The body voltages generated by register tree 61B are amplified by amplifier 435 such that final body voltages PBODY2 and PBODY2 are supplied to macro block 200. Body voltages PBODY1 represent body voltages to be applied to the PMOS transistors of macro block 100 and body voltages NBODY1 represent body voltages to be applied to NMOS transistors of macro block 100. Body voltages PBODY2 represent body voltages to be applied to PMOS transistors of macro block 200 and body voltages NBODY2 represent body voltages to be applied to NMOS transistors of macro block 200.
FIG. 9 is a circuit diagram of register trees 61A and 61B illustrated in FIG. 6. Each register tree 61A and 61B includes a voltage divider 91, a first switch circuit 93, and a second switch circuit 95. Voltage divider 91 is connected between a first reference voltage VDDH and a second reference voltage VDDL and divides a voltage range between the first reference voltage VDDH and the second reference voltage VDDL into a plurality of output voltages O1-O8. The first switch circuit 93 selects one voltage from among output voltages O1-O4 of voltage divider 91. This selected output voltage is supplied as body voltage PBODY to the PMOS transistors of the corresponding macro block (for example, macro block 100 or 200 illustrated in FIG. 4) via amplifier 435-1 in response to the converted output bits /ADR0 through /ADRn. Second switch circuit 95 selects one voltage from among the output voltages O5-O8 of voltage divider 91. This selected output voltage is supplied as a body voltage NBODY to the NMOS transistors of the corresponding macro block via amplifier 435-2 in response to output bits ADR0-ADRn. By appropriately configuring voltage divider 91, first switch circuit 93, and second switch circuit 95, body voltages PBODY and NBODY are generated having the exemplary values illustrated in FIG. 4 corresponding to output bits ADR0-ADRn of decoder 431. Voltage divider 91 includes a plurality of resistors R1-R8 which are connected in series between first reference voltage VDDH and second reference voltage VDDL. Resistors R1-R8 may be, for example, PMOS transistors.
First switch circuit 93 includes a plurality of PMOS switches S31-S34 connected between output nodes O1-O4 of voltage divider 91. Switch circuit 93 also includes first common node N1 where the converted output bits /ADR0-/ADRn are applied to the gates of PMOS switches S31-S34 and a plurality of first latch circuits L31-L34 which are connected to the gates of the PMOS switches S31-S34. Second switch circuit 95 includes a plurality of NMOS switches S51-S54 connected between output nodes O5-O8 of voltage divider 91. Circuit 95 also includes second common node N2 where the output bits ADRO-ADRn are applied to the gates of NMOS transistors S51-S54 and a plurality of second latch circuits L51-L54 connected to the gates of the NMOS switches S51-S54. The latch circuits L31-L34 and L51-L54 are connected to the gates of switches S31-S34 and S51-S54 so that the body voltages PBODY and NBODY of a macro block (for example, macro block 200) are maintained when a different macro block (for example, macro block 100) is controlled.
The body biasing control circuit in accordance with the present invention does not require a conventional monitoring circuit for checking a threshold voltage and can be implemented as a small-sized integration circuit. In addition, the body biasing control circuit can be shared by a plurality of macro blocks and can independently control body voltages associated with the plurality of macro blocks. Since body voltages appropriate for the operating state of each macro block are directly generated according to indexes; the time required for biasing can be reduced as compared with conventional techniques.
Although the present invention has been described in connection with the embodiment of the present invention illustrated in the accompanying drawings, it is not limited thereto. It will be apparent to those skilled in the art that various substitution, modifications and changes may be thereto without departing from the scope and spirit of the invention.