Patent Application
20110316914
Solid ink jet printers generally have print head driver or controller chips that control the voltages sent to the actuators. The actuators convert the voltages received into mechanical energy that pushes ink drops out of apertures (or “jets”) to form images on a print surface. Control of the actuators controls the sizes of the drops and the velocity at which they exit the apertures.
Manufacturing variances can affect both the size and the velocity of ink drops. Typically, print heads undergo testing after manufacture to determine the nature and magnitude of the variances. A process referred to as “normalization” adjusts the voltage applied to each actuator corresponding to each jet to cause the jet to expel ink drops of a standard size and at a standard velocity within some tolerance range. Typically, the normalization process employs at least one transistor as part of the driver chip circuitry, typically on the outputs.
Within the semiconductor layers used to form the transistors “body diodes” generally form. The “body diodes” consists of PN junctions between the source/channel and drain regions of the transistors, typically field-effect transistor (FETs), such as in MOSFETs (metal oxide semiconductor FETs). The body diodes form base and emitter terminals of parasitic, bi-polar junction transistors. The collector terminals of these bi-polar junction transistors may be the chip substrate.
The body diodes conduct current during the trailing edges of high-voltage pulses used in the actuation circuitry. This current causes parasitic current to the chip substrate, creating unwanted power dissipation within the chip. Newer trench-isolated silicon chip processes, while advantageous for print head driver chip fabrication, have even higher gain in these parasitic bi-polar transistors, resulting in higher parasitic current flowing to the chip substrate.
An ink jet printer generally consists of an array of ejection ports such as 18, also referred to as nozzles or jets, each of which expel ink in accordance with a signal from the controller/driver such as 16. The print head generally draws its ink from an ink supply such as 14, which may consist of liquid ink, or of solid ink that melts and becomes liquid.
A control module, which may take the form of a single integrated circuit ‘chip,’ or may consist of several chips, determines which jets will expel ink at what intervals by sending signals to actuators associated with the jets. The data used to send those signals comes from image data, either sent to the printer electronically, such as through fax or from a computing device, or from image acquisition by scanning, such as making copies. The signals typically consist of voltage pulses sent to the actuators in the print head.
The transducers convert the electrical signals into some form of mechanical force that cause the jets to expel ink. In some ink jets, the transducers consist of resistors that become hot when they receive the voltage, causing bubbles to form around them. The expansion of the bubbles forces ink out of the jets. In another example, the transducers consist of piezoelectric elements that compress ink within body chambers, causing ink to exit the jets.
Since a typical print head has hundreds or thousands of jets, each with their own transducer, the print heads consume relatively high amount of power. Inefficiencies in the system that result in loss of power in turn result in a lower efficiency, higher cost print system. One such inefficiency lies in body diodes in the output transistors. Each jet receives an output signal from a driver circuit in which a transistor controls the transmission of the output signal. Each transistor has a body diode that dissipates power.
A body diode results from a by product of the semiconductor manufacturing process used to manufacture the output circuit for the voltage signal that activates the transducers. Typically, a body diode acts a bi-polar junction transistor with the base and emitter terminals formed by the PN junction and the collector being the chip substrate. These body diodes become forward biased, conducting current essentially into the chip substrate, causing the chip substrate to absorb power. This essentially ‘wastes’ the power, making the device inefficient.
In the below discussion, the output circuit 22 takes the form of a P-channel field effect transistor (PFET), but no limitation is intended to this structure nor should any be implied. The drive circuitry may be implemented in the opposite logic, resulting in a NFET being the output circuit, etc. Other types of transistors may also have similar effects to the body diode.
The signals Vpp_sel (V1) and Vss_sel (V2) are the low-voltage digital inputs to the logic circuitry. Vout is the high-voltage output to the print head element, the ejection port, nozzle or jet. For purposes of this circuit, a capacitor C5 simulates the jet load. The PFET U26 and NFET U11 form the output circuit.
During the rising edges of the pulses from VPP, the high-side output circuit 22, turns off at the appropriate time to leave the desired positive voltage level on Vout. During the subsequent falling edge of the VPP pulse, the body diode associated with the PFET becomes active and begins to conduct current. This causes the voltage at the jet, Vout, to return to 0 V. Typically, designers rely on the body diode becoming forward biased and conducting current since that pulls the voltage to 0. However, controlling the amount of current it conducts becomes important to reduce the parasitic power dissipation. If the body diode conducts too much current it will waste power
By turning the high-side output circuit 22 back on, the amount of current the body diode conducts becomes reduced, alleviating the parasitic power dissipation. Generally, the output circuit should remain in the on state, regardless of the drop in the current conducted by the body diode. Otherwise, the current may drop sufficiently to turn the output circuit off, initiating an oscillation in the circuit.
Having seen a more simplified version to assist in understanding the embodiments, the discussion now turns to a more detailed diagram shown in
In the embodiment of
The forward bias detection circuit 32 detects when the body diode in PFET 22 becomes forward biased, which will be discussed in more detail with regard to
The logic gate 34 generates a signal p4 when the p_on_n and p3_n signals are both low. One should note that the gate shown here is an OR gate with inverted inputs (NAND gate), but could be implemented in many other ways. The signal p4 will generally be a ‘logic level’ signal, where the driving voltage for the PFET needs to be considerably higher. The gate drive level translator 36 translates the logic high signal to an appropriate voltage to drive the gate of the PFET 22 as signal pg, for example, 9V below Vpp. This signal will cause the PFET to turn ON. The p_on_n signal will remain low (true) until the signal falling goes low (false). This avoids oscillation. When the PFET 22 turns on, it conducts current, reducing the body diode current and in turn reducing the parasitic current to the chip substrate.
The bias voltage vpp0a, on the gate of PFET U87, is held constant at approximately one PFET threshold voltage below Vpp. Therefore, when node pf on the drain of U87 rises above Vpp, the node pb will be pulled up. When node pb overcomes the pull down current of the NFET U66, node pb goes high. This pulls node p_on_n low, turning on the output PFET 22. The NAND gate of U77/U78 and U76/U75 for p_on_n and pb are cross-coupled through inverter U71/U89 to keep p_on_n low until the enabling signal falling goes low (false).
This cross-coupled gate/inverter pair acts as a latch to stabilize the state of the output PFET 22 as ON. Otherwise, the act of turning on the PFET 22 may reduce the body diode current sufficiently to cause the PFET to turn OFF. Once the PFET turns OFF, the body diode being forward biased may cause it to turn back ON, initiating an oscillating sequence.
In summary, the circuit turns on the high-side VPP output circuit when the associated body diode becomes, or is about to become, forward biased. The forward biasing occurs when the voltage on the output of the output circuit, in this case the drain of PFET 22, rises above the VPP supply voltage on the source of the PFET 22. The output circuit only turns on again during the falling edges of VPP, avoiding un-intentional turn-on events due to offset voltages or small noise signals on VPP or the jet output. The circuit also avoids oscillation due to the reduction in body-diode current once the output circuit turns on again.
As mentioned above, the signal falling enables the detection circuit 38 of
The signal falling must be true during the falling edges of VPP pulses, detected by the detection circuit 54. The detection circuit 54 in this embodiment causes the signal to go true on the falling edge of the VPP pulse. The circuit detects the falling edges when Vpp has dropped by some predetermined margin, such as −1 or −2 volts, and that drop lasts for at least some predetermined minimum time, such as 30 nanoseconds. This voltage margin and minimum time prevent unintended triggering of signal falling due to momentary spikes or overshoot on Vpp.
The disabling circuit 56 acts to disable the falling signal when the level of VPP nears that of Vss. In this example, the falling signal is disabled when VPP reaches 3 V above Vss. This ensures that the output PFET 22 is OFF before the output NFET 46 turns ON, in the circuit of
Returning momentarily to
In
The example of
In this manner, forward biasing of the body diode on the output PFET is detected. The detection then causes the output PFET to turn ON to reduce the body diode current and reduce parasitic current to the chip substrate, reducing the wasted power. The detection is enabled and disabled by a global signal falling, and the state of the detection is latched to prevent oscillation.
It will be appreciated that several of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. Also that various presently unforeseen or unanticipated alternatives, modifications, variations, or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.
