Patent Application
20230329054
This application claims priority to Korean Patent Application No. 10-2022-0044749, filed on Apr. 11, 2022, and all the benefits accruing therefrom under 35 U.S.C. § 119, the entire contents of which are hereby incorporated by reference.
The present disclosure herein relates to a display device, and more particularly, to a display device including a flexible circuit board.
Electronic devices, such as smartphones, tablet computers, notebook computers, vehicle navigation devices, and smart televisions, are developed. Such electronic devices are provided with display devices so as to provide information to outside the electronic devices, such as to a user of the electronic devices.
In order to satisfy a user experience (UX) and a user interface (UI), display devices with various shapes are developed. Among the display devices, flexible display devices have been actively developed.
The present disclosure provides a display device having a reduced bezel region.
An embodiment of the invention provides a display device including a window including a bezel region and a transmission region, an upper film disposed below the window and overlapping the bezel region and the transmission region, a display module disposed below the upper film and including a pad region coupled to a lower surface of the upper film in the bezel region, a lower film disposed below the display module and exposing the pad region to outside the display module, a flexible circuit board disposed below the lower film and bonded to the pad region of the display module, and a resin structure which bonds the flexible circuit board to the display module. The display module includes a base layer in which a first open region corresponding to the pad region is defined, a pixel disposed on the base layer, and a signal line which includes a pad portion overlapping the first open region, is disposed on the base layer, and electrically connects the pixel and the flexible circuit board.
In an embodiment, the pad portion may be exposed to outside the base layer through the first open region.
In an embodiment, the display module may further include a shield electrode, and the pixel may include a transistor including a semiconductor pattern and a gate, and a light emitting element which is connected to the transistor. The shield electrode may be disposed below the semiconductor pattern and overlap the semiconductor pattern.
In an embodiment, the display module may further include a pad electrode disposed on the same layer as the shield electrode, overlapping the pad portion, and disposed below the pad portion. The pad electrode may be electrically connected to the pad portion and the flexible circuit board.
In an embodiment, the display module may further include a sub-base layer disposed below the signal line and disposed above the base layer, at least one inorganic layer disposed between the sub-base layer and the base layer, and a pad electrode disposed between the sub-base layer and the base layer. The pad electrode may be electrically connected to the pad portion and the flexible circuit board.
In an embodiment, the display module may further include a sub-base layer disposed below the signal line and disposed above the base layer, and at least one inorganic layer disposed between the sub-base layer and the base layer. The pad portion of the signal line may be disposed between the sub-base layer and the base layer.
In an embodiment, a second open region corresponding to the pad region may be defined in the lower film.
In an embodiment, a side surface of the display module, a side surface of the upper film, and a side surface of the lower film may be in contact with the resin structure.
In an embodiment, a side surface of the pad portion may be in contact with the resin structure.
In an embodiment, the display device may further include a cover panel disposed below the lower film, and a driving chip mounted on the flexible circuit board. A cavity may be defined in a lower surface of the cover panel, and the driving chip may be inserted into the cavity.
In an embodiment, the display module may further include an input sensor disposed on the base layer.
In an embodiment, the display module may further include an anti-reflection member disposed on the input sensor. The anti-reflection member may include a color filter that is disposed to correspond to the pixel.
In an embodiment of the invention, a display device may include a window including a bezel region and a transmission region, a display module disposed below the window and including a pad region overlapping the bezel region, an upper member disposed between the window and the display module and non-overlapping the pad region, a first resin structure disposed between the window and the display module to bond the window and the display module, and overlapping the pad region, a lower film disposed below the display module and exposing the pad region to outside the display module, a flexible circuit board disposed below the lower film and bonded to the pad region of the display module, and a second resin structure which bonds the flexible circuit board to the display module. The display module may include a base layer in which a first open region corresponding to the pad region is defined, a pixel disposed on the base layer, and a signal line including a pad portion which is disposed on the base layer, electrically connects the pixel and the flexible circuit board, and overlaps the first open region.
In an embodiment, the upper member may include an adhesive layer that bonds the window and the display module.
In an embodiment, the pad portion may be exposed to outside the base layer through the first open region.
In an embodiment, a second open region corresponding to the pad region may be defined in the lower film, and the flexible circuit board may be bonded to the pad region through the second open region.
In an embodiment, a side surface of the display module and a side surface of the lower film may be in contact with the second resin structure.
In an embodiment, a side surface of the pad portion may be in contact with the second resin structure.
In an embodiment, the display device may further include a sub-base layer disposed below the signal line and disposed above the base layer, at least one inorganic layer disposed between the sub-base layer and the base layer, and a pad electrode disposed between the sub-base layer and the base layer.
In an embodiment, the pad electrode may be electrically connected to the pad portion and the flexible circuit board.
In an embodiment, the display module may further include a sub-base layer disposed below the signal line and disposed above the base layer, and at least one inorganic layer disposed between the sub-base layer and the base layer. The pad portion of the signal line may be disposed between the sub-base layer and the base layer.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the invention. In the drawings:
The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It will be understood that in this specification, when an element (or region, layer, section, etc.) is referred to as being related to another element such as being “on”, “connected to” or “coupled to” another element, it can be disposed directly on, connected or coupled to the other element or a third intervening element may be disposed between the elements. In contrast, when an element (or region, layer, section, etc.) is referred to as being related to another element such as being “directly on”, “directly connected to” or “directly coupled to” another element, no third intervening element is disposed between the elements. As being related “directly,” elements may form an interface therebetween.
Like reference numbers or symbols refer to like elements throughout. As used herein, a reference number may indicate a singular element or a plurality of the element. For example, a reference number labeling a singular form of an element within the drawing figures may be used to reference a plurality of the singular element within the text of specification.
In addition, in the drawings, the thickness, the ratio, and the dimension of elements are exaggerated for effective description of the technical contents. The term “and/or” includes one or more combinations which may be defined by relevant elements.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element without departing from the teachings of the invention, and similarly, a second element could be termed a first element. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” In addition, the terms, such as “below”, “beneath”, “on” and “above”, are used for explaining the relation of elements shown in the drawings. The terms are relative concept and are explained based on the direction shown in the drawing.
It will be further understood that the terms such as “includes” or “has”, when used herein, specify the presence of stated features, numerals, steps, operations, elements, parts, or the combination thereof, but do not preclude the presence or addition of one or more other features, numerals, steps, operations, elements, parts, or the combination thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.
Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.
Referring to
The display surface DS may include a display region DA and a non-display region NDA which is adjacent to the display region DA. The display region DA may display the image IM, and the non-display region NDA may not display the image IM. The non-display region NDA may surround the display region DA in a plan view (e.g., a view of the plane defined by the first direction DR1 and the second direction DR2 crossing each other. However, an embodiment of the invention is not limited thereto, and the shape (e.g., a planar shape) of the display region DA and the shape (e.g., a planar shape) of the non-display region NDA may be changed.
Hereinafter, a direction substantially perpendicularly crossing a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The third direction DR3 serves as a reference direction for distinguishing a front surface and a rear surface of each member. In the present disclosure, the term “on a plane” may be defined as being seen in the third direction DR3. Hereinafter, the first to third directions DR1, DR2 and DR3 are directions respectively indicated by first to third directional axes and denoted as like reference numbers or symbols. A thickness of the electronic device ED and various components or layers thereof may be defined along the third direction DR3 (e.g., a thickness direction).
In an embodiment of the invention, the electronic device ED may be a foldable electronic device that is capable of being folded with respect to a folding axis (e.g., is foldable about a folding axis). The folding axis may be parallel to the first direction DR1 or the second direction DR2, and a folding region at which the electronic device ED is foldable may be defined in a portion of the display region DA. The electronic device ED may be in-folded so that portions of the display region DA face each other, or may be out-folded so that portions of the display region DA face away from each other. Various components and/or layers of the electronic device ED may be foldable together with each other, without being limited thereto.
As illustrated in
The display device DD generates an image IM and detects an external input. The display device DD includes a window WM, an upper member UM (e.g., an upper layer), a display module DM, a lower member LM (e.g., a lower layer), a flexible circuit board FCB, and a driving chip DIC. The upper member UM includes members disposed above the display module DM, and the lower member LM includes members disposed below the display module DM, along the thickness direction.
The window WM provides (or defines) a front surface of the electronic device ED. The window WM includes a transmission region TA and a bezel region BA. The display region DA and the non-display region NDA of the display surface DS illustrated in
The display module DM may include at least a display panel DP.
The display panel DP is not particularly limited, and may include, for example, an organic light emitting display panel or an inorganic light emitting display panel. The display panel DP includes a display region DP-DA and a non-display region DP-NDA respectively corresponding to the display region DA and the non-display region NDA which are illustrated in
A pad region PA of the display panel DP is disposed in the non-display region DP-NDA and at one side of the display region DP-DA. The pad region PA is a region at which the display panel DP is electrically bonded (or connected) to a flexible circuit board FCB to be described later.
The upper member UM may include a protective film and/or an optical film. The optical film may include a polarizer and a retarder to reduce the reflectance of external light. The lower member LM may include a protective film, which protects the display panel DP, a support member, which supports the display panel DP, a digitizer, etc. The upper member UM and the lower member LM will be described later in detail.
The flexible circuit board FCB illustrated in
The driving chip DIC may be mounted on the flexible circuit board FCB. The driving chip DIC may include driving circuits, for example, a data driving circuit, for driving the pixels PX of the display panel DP.
The electronic module EM may include a control module, a wireless communication module, an image input module, a sound input module, a sound output module, a memory, an external interface module, and so on. The electronic module EM may include a main circuit board, and the modules may be mounted on the main circuit board and/or electrically connected to the main circuit board through a flexible circuit board FCB. The electronic module EM is electrically connected to the power supply module PSM.
Although not separately illustrated, the electronic device ED may further include an electro-optical module. The electro-optical module may be an electronic component for outputting or receiving an optical signal. The electro-optical module may include a camera module and/or a proximity sensor. The camera module may capture an external image through a region of the display panel DP.
The housing HM illustrated in
The window WM may include a base substrate BS and a bezel pattern BM which is disposed on a lower surface of the base substrate BS. The lower surface may be closest to the display module DM. The base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multilayer structure. The base substrate BS may include a thin film glass substrate, a protective film disposed on the thin film glass substrate, and an adhesive layer which bonds the thin film glass substrate and the protective film.
The bezel pattern BM may be formed or provided as a colored light-shielding film using, for example, a coating method. The bezel pattern BM may include a base material and a dye or pigment which is combined with the base material. The bezel pattern BM overlaps the non-display region NDA illustrated in
The upper member UM may include an upper film UF. The upper film UF may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, triacetylcellulose, polymethylmethacrylate, or polyethylene terephthalate.
The upper film UF may absorb external impact applied to or from a front surface of the display device DD (e.g., an impact absorbing layer). In an embodiment of the invention, the display module DM may include a color filter which replaces a polarizing film as an anti-reflection member, thereby reducing the impact strength applied to the front surface of the display device DD. The upper film UF may compensate for the impact strength reduced due to application of the color filter.
The upper film UF overlaps the bezel region BA and the transmission region TA. The upper film UF may overlap only a partial region of the bezel region BA. A portion of the bezel pattern BM may be exposed from the upper film UF. In an embodiment of the invention, the upper film UF may be omitted.
The upper member UM may further include a first adhesive layer AL1, which bonds the upper film UF and the window WM to each other, and a second adhesive layer AL2 which bonds the upper film UF and the display module DM to each other. The first adhesive layer AL1 and the second adhesive layer AL2 may each be a pressure sensitive adhesive film (PSA) or an optically clear adhesive (OCA). Adhesive layers to be described herebelow may also include the same adhesive as the first adhesive layer AL1.
The display module DM is disposed below the upper film UF. The display module DM overlaps the bezel region BA and the transmission region TA. The display module DM may fully overlap the upper film UF in the bezel region BA. A side surface of the display module DM may be aligned with a side surface of the upper film UF at the end of the electronic device. On a plane, a corner of the display module DM may be aligned with a corner of the upper film UF.
At least the pad region PA of the display module DM may overlap the upper film UF, in the bezel region BA. The pad region PA overlapping a lower surface of the upper film UF may be bonded to the upper film UF at the lower surface of the upper film UF, via the second adhesive layer AL2. The pad region PA overlaps the upper film UF, and the pad region PA is bonded to the upper film UF so that the upper film UF may sufficiently support the pad region PA when the flexible circuit board FCB is bonded to the pad region PA. This will be described later in detail.
The lower member LM may include a lower film PF, a cover panel CP, a third adhesive layer AL3, and a fourth adhesive layer AL4. The lower member LM may further include a support plate and a digitizer, which are not illustrated.
The lower film PF may be disposed below the display module DM, and may be bonded to the display module DM, at a lower surface of the display module DM, via the third adhesive layer AL3. The lower surface may be furthest from the window WM. The lower film PF may protect a lower portion of the display module DM. The lower film PF may include a flexible synthetic resin film. For example, the lower film PF may include polyethylene terephthalate or polyimide, and is not limited thereto.
The lower film PF exposes at least the pad region PA, to outside the lower film PF. In an embodiment, the lower layer (e.g., the lower film PF) is non-overlapping with the pad region PA. The lower film PF may have a smaller area (e.g., planar area) than the display module DM. For example, the lower film PF may overlap only the display region DA.
In an embodiment, the lower film PF may have substantially the same area as the display module DM. An open region PF-OP (hereinafter referred to as a first open region) corresponding to the pad region PA, may be defined in the lower film PF. Although the lower film PF entirely protects the lower surface of the display module DM, the first open region PF-OP is defined to expose the pad region PA to outside the lower film PF so that the flexible circuit board FCB is allowed to approach and be connected to the display module DM at the pad region PA.
The planar shape of the first open region PF-OP is not particularly limited. The first open region PF-OP may have a notch shape. In an embodiment of the invention, edges defining the first open region PF-OP may have a closed line shape in the plan view.
As illustrated in
A cavity CP-C may be defined in (or by portions of) the cover panel CP. The cavity CP-C may be a recess which is recessed in a direction toward the display module DM, from a lower surface of the cover panel CP. The flexible circuit board FCB which is bent along an end surface of the lower film PF and the cover panel CP, may dispose the driving chip DIC inserted into the cavity CP-C. The cavity CP-C may remove or compensate for a stepped structure or an irregular portion formed (or provided) by the driving chip DIC together with the flexible circuit board FCB. The cavity CP-C is not limited to the cavity CP-C of the cover panel CP as long as being defined in a member disposed on a lowest side of the lower member LM.
The cover panel CP, which is non-aligned with the lower film PF in the bezel region BA, is illustrated as an example, but an embodiment of the invention is not limited thereto. The cover panel CP may have substantially the same shape and/or planar area as the lower film PF.
The support plate may be disposed below the cover panel CP. The support plate may include a metal material with high strength. The support plate may include a reinforced fiber composite material. The support plate may include a reinforced fiber which is disposed inside a matrix part of the support plate. The reinforced fiber may be a carbon fiber or a glass fiber. The matrix part may include a polymer resin. The matrix part may include a thermoplastic resin. For example, the matrix part may include a polyamide-based resin or a polypropylene-based resin. For example, the reinforced fiber composite material may be a carbon fiber reinforced plastic (CFRP) or a glass fiber reinforced plastic (GFRP).
The resin structure LS bonds the flexible circuit board FCB to the display module DM, at an end surface of the display module DM. The resin structure LS may be extended along and cover the side surface (or end surface) of the upper film UF, the side surface of the display module DM, and a side surface of the cover panel CP. The resin structure LS is disposed inside the window WM, on a plane. The resin structure LS does not protrude outward from the window WM (e.g., further than an end surface of the window WM) so that interference due to the resin structure LS may not occur when the housing HM (see
The resin structure LS may fill the first open region PF-OP. The resin structure LS may be formed using an insert-molding method. The resin structure LS may include an acryl-based resin, and the type of the resin is not particularly limited. The resin structure LS may include polypropylene (PP), polyethylene (PE), polystyrene (PS), acrylonitrile-styrene (AS), or polymethyl methacrylate (PMMA).
Referring to
The base layer 110 may provide a base surface on which the circuit layer 120 is disposed. The base layer 110 may be a flexible substrate that is bendable, foldable, or rollable. The base layer 110 may be a glass substrate, a metal substrate, a polymer substrate, or the like. However, an embodiment of the invention is not limited thereto, and the base layer 110 may be an inorganic layer, an organic layer, or a composite material layer.
The base layer 110 may have a multilayer structure. For example, the base layer 110 may include a first synthetic resin layer, a second synthetic resin layer, and inorganic layers disposed between the first and second synthetic resin layers. Each of the first and second synthetic resin layers may include a polyimide-based resin, and is not particularly limited.
The circuit layer 120 may be disposed on the base layer 110. The circuit layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, and so on.
The light emitting element layer 130 may be disposed on the circuit layer 120. The light emitting element layer 130 may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED or a nano LED. The light emitting layer, alone or together with the circuit layer 120, may define a display element layer which generates an image IM, without being limited thereto.
The encapsulation layer 140 may be disposed on the light emitting element layer 130. The encapsulation layer 140 may protect the light emitting element layer 130 from moisture, oxygen, and foreign substances such as dust particles. The encapsulation layer 140 may include at least one inorganic layer. The encapsulation layer 140 may include a stacked structure in which an inorganic layer/an organic layer/an inorganic layer are stacked.
The input sensor ISP may be disposed directly on the display panel DP. The input sensor ISP may detect a user's input by using a capacitance method. The display panel DP and the input sensor ISP may be formed through a continuous process. Here, “being disposed directly” may mean that a third component is not disposed between the input sensor ISP and the display panel DP. That is, a separate adhesive layer may not be disposed between the input sensor ISP and the display panel DP. As a separate layer or third element is not disposed between the input sensor ISP and the display panel DP, the input sensor ISP and the display panel DP may contact each other.
The anti-reflection layer ARL may be disposed directly on the input sensor ISP. The anti-reflection layer ARL may reduce the reflectance of external light incident from the outside of the display device DD. The anti-reflection layer ARL may include color filters. The color filters may have a predetermined arrangement. For example, the color filters may be arranged while considering emission colors of the pixels PX included in the display panel DP. In addition, the anti-reflection layer ARL may further include a black matrix adjacent to the color filters.
In an embodiment of the invention, the anti-reflection layer ARL may be replaced by a polarizing film. The polarizing film may be bonded to the input sensor ISP through an adhesive layer.
Referring to
The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to Elm, first and second control lines CSL1 and CSL2, and a power line PL. Here, ‘m’ and ‘n’ are natural numbers. The pixels PX may be connected to the scan lines SL1 to SLm, the data lines DL1 to DLn, and the emission lines EL1 to ELm.
The scan lines SL1 to SLm may extend in the second direction DR2 to be connected to the scan driving unit SDV. The emission lines EL1 to ELm may extend in the first direction DR1 to be connected to the emission driving unit EDV.
The power line PL may include a part extending in the second direction DR2 and a part extending in the first direction DR1. The part extending in the first direction DR1 and the part extending in the second direction DR2 may be disposed on different layers. The power line PL may supply a first voltage to the pixels PX.
Each of the data lines DL1 to DLn extends in the second direction DR2, and has an end disposed in a pad region PA. The data lines DL1 to DLn may be electrically connected to the driving chip DIC. The first control line CSL1 is connected to the scan driving unit SDV, and has an end (e.g., a distal end) disposed in the pad region PA. The second control line CSL2 is connected to the emission driving unit EDV, and has an end disposed in the pad region PA.
A pixel circuit PC, which drives the light emitting element LD, may include a plurality of transistors.
Referring to
Referring to
A first shield electrode BMLa may be disposed on the barrier layer 10br. The first shield electrode BMLa may include a metal. The first shield electrode BMLa may include molybdenum (Mo), a molybdenum-containing alloy, titanium (Ti), or a titanium-containing alloy, which has good heat resistance. The first shield electrode BMLa may receive a bias voltage. The first shield electrode BMLa may receive a first power supply voltage ELVDD. The first shield electrode BMLa may block an electrical potential caused by polarization from affecting the silicon transistor S-TFT. The first shield electrode BMLa may block external light from arriving at the silicon transistor S-TFT. In an embodiment of the invention, the first shield electrode BMLa may be a floating electrode that is isolated (e.g., electrically isolated) from another electrode or wiring.
A buffer layer 10bf may be disposed on the barrier layer 10br. The buffer layer 10bf may prevent metal atoms or impurities from diffusing from the base layer 110 into a first semiconductor pattern SC1 thereabove. The buffer layer 10bf may include at least one inorganic layer. The buffer layer 10bf may include a silicon oxide layer and a silicon nitride layer.
The first semiconductor pattern SC1 may be disposed on the buffer layer 10bf. The first semiconductor pattern SC1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first semiconductor pattern SC1 may include low-temperature polysilicon.
The first semiconductor pattern SC1 may have different electrical properties at various regions, depending on whether the first semiconductor pattern SC1 is doped or not at such regions. The first semiconductor pattern SC1 may include a first region with high conductivity and a second region with low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with the P-type dopant, and an N-type transistor may include a doped region doped with the N-type dopant. The second region may be a non-doped region or may be doped with the doping concentration lower than that of the first doped region.
The conductivity of the first region may be higher than the conductivity of the second region, and the first region may substantially serve as an electrode or a signal line. The second region may substantially correspond to a channel region (or active region) of a transistor. In other words, one portion of the first semiconductor pattern SC1 may be a channel of the transistor, another portion may be a source or a drain of the transistor, and still another portion may be a connection electrode or a connection signal line.
A source region SE1, a channel region AC1 (or active region), and a drain region DE1 of the silicon transistor S-TFT may be formed from the first semiconductor pattern SC1. The source region SE1 and the drain region DE1 may extend from the channel region AC1 in opposite directions, on a cross section.
A first insulating layer 10 may be disposed on the buffer layer 10bf. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may be a single-layered silicon oxide layer. Not only the first insulating layer 10, but also an inorganic layer of a circuit layer 120 to be described later may have a single-layer structure or a multilayer structure, and may include at least one among the materials described above. However, an embodiment of the invention is not limited thereto.
A gate GT1 of the silicon transistor S-TFT is disposed on the first insulating layer 10. The gate GT1 may be a portion of a metal pattern, that is, a respective pattern of a metal layer including a plurality of metal patterns. The gate GT1 overlaps the channel region AC1. The gate GT1 may function as a mask in a process for doping the first semiconductor pattern SC1. A first electrode CE10 of a storage capacitor Cst is disposed on the first insulating layer 10. Unlike what is illustrated in
A second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate GT1. Although not illustrated, an upper electrode overlapping the gate GT1 may be disposed on the second insulating layer 20. A second electrode CE20 overlapping the first electrode CE10 may be disposed on the second insulating layer 20.
A second shield electrode BMLb is disposed on the second insulating layer 20. The second shield electrode BMLb may be disposed to correspond to a lower portion of the oxide transistor O-TFT. In an embodiment of the invention, the second shield electrode BMLb may be omitted. According to an embodiment of the invention, the first shield electrode BMLa may extend from the silicon transistor S-TFT and along the base layer 110 to the lower portion of the oxide transistor O-TFT, and thus replace the second shield electrode BMLb.
A third insulating layer 30 may be disposed on the second insulating layer 20. A second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include an oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnOx), or indium oxide (In2O3).
The oxide semiconductor may include a plurality of regions classified according to whether the transparent conductive oxide is reduced or not. A region in which the transparent conductive oxide is reduced (hereinafter referred to as a reduced region), has higher conductivity than a region in which the transparent conductive oxide is not reduced (hereinafter referred to as a non-reduced region). The reduced region substantially serves as a source/drain or a signal line of a transistor. The non-reduced region substantially corresponds to a semiconductor region (or channel) of the transistor. In other words, one portion of the second semiconductor pattern SC2 may be the semiconductor region of the transistor, another portion may be the source/drain region of the transistor, and still another portion may be a signal transfer region.
A fourth insulating layer 40 may be disposed on the third insulating layer 30. As illustrated in
The gate GT2 of the oxide transistor O-TFT is disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a portion of a metal pattern. The gate GT2 of the oxide transistor O-TFT overlaps the channel region AC2.
A fifth insulating layer 50 may be disposed on the fourth insulating layer 40, and the fifth insulating layer 50 may cover the gate GT2. Each of the first insulating layer 10 to the fifth insulating layer 50 may be an inorganic layer.
A first connection electrode CNE1 may be disposed on the fifth insulating layer 50. The first connection electrode CNE1 may be connected to the drain region DE1 of the silicon transistor S-TFT through a contact hole passing through the first to fifth insulating layers 10, 20, 30, 40 and 50.
A sixth insulating layer 60 may be disposed on the fifth insulating layer 50. A second connection electrode CNE2 may be disposed on the sixth insulating layer 60. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through (or at) a contact hole passing through the sixth insulating layer 60. A data line DL may be disposed on the sixth insulating layer 60. A seventh insulating layer 70 may be disposed on the sixth insulating layer 60, and cover the second connection electrode CNE2 and the data line DL. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.
The light emitting element LD may include an anode AE (or first electrode), an emission layer EL, and a cathode CE (or second electrode). The anode AE of the light emitting element LD may be disposed on the seventh insulating layer 70. The anode AE may be a (semi-)transmissive electrode or a reflective electrode.
A pixel defining layer PDL may be disposed on the seventh insulating layer 70. The pixel defining layer PDL may include the same material and be formed through the same process. The pixel defining layer PDL may have a light absorbing property, and for example, the pixel defining layer PDL may have a black color. The pixel defining layer PDL may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include a carbon black, a metal such as chrome, or an oxide thereof. The pixel defining layer PDL may correspond to a light shielding pattern having a light shielding property.
The pixel defining layer PDL may cover a portion of the anode AE. For example, an opening portion PDL-OP exposing a portion of the anode AE to outside the pixel defining layer PDL, may be defined in (or by portions of) the pixel defining layer PDL.
Although not illustrated, a hole control layer may be disposed between the anode AE and the emission layer EL. The hole control layer may include a hole transport layer and further include a hole injection layer. An electron control layer may be disposed between the emission layer EL and the cathode CE. The electron control layer may include an electron transport layer and further include an electron injection layer. The hole control layer and the electron control layer may be formed, in common, in the display region DP-DA (see
An encapsulation layer 140 may be disposed on a light emitting element layer 130. The encapsulation layer 140 may include an inorganic encapsulation layer 141, an organic encapsulation layer 142, and an inorganic encapsulation layer 143, which are stacked in sequence. However, layers constituting the encapsulation layer 140 are not limited thereto.
The inorganic encapsulation layers 141 and 143 may protect the light emitting element layer 130 from moisture and oxygen, and the organic encapsulation layer 142 may protect the light emitting element layer 130 from foreign substances such as dust particles. The inorganic encapsulation layers 141 and 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. The organic encapsulation layer 142 may include an acrylic organic layer, and is not limited thereto.
An input sensor ISP may be disposed on a display panel DP. The input sensor ISP may include at least one conductive layer and at least one insulating layer. In this embodiment, the input sensor ISP may include a first insulating layer 210, a first conductive layer 220, a second insulating layer 230, and a second conductive layer 240.
The first insulating layer 210 may be disposed directly on the display panel DP. The first insulating layer 210 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, or silicon oxide. Each of the first conductive layer 220 and the second conductive layer 240 may have a single-layer structure or a multilayer structure in which layers are stacked along the third direction DR3. The first conductive layer 220 and the second conductive layer 240 may include conductive lines that define a mesh-shaped electrode. The mesh-shaped electrode may include the conductive lines as solid portions spaced apart from each other, and spaces defined therebetween, without being limited thereto. The conductive line of the first conductive layer 220 and the conductive line of the second conductive layer 240 may be connected to each other through a contact hole passing through the second insulating layer 230, or may not be connected to each other. A connection relationship between the conductive line of the first conductive layer 220 and the conductive line of the second conductive layer 240 may be determined depending on the type of a sensor formed as the input sensor ISP.
When having a single-layer structure, each of the first conductive layer 220 and the second conductive layer 240 may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnOx), or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowire, graphene, etc.
When having a multilayer structure, each of the first conductive layer 220 and the second conductive layer 240 may include metal layers. The metal layers may have, for example, a three-layer structure including titanium/aluminum/titanium. The conductive layer having a multilayer structure may include at least one metal layer and at least one transparent conductive layer. The second insulating layer 230 may be disposed between the first conductive layer 220 and the second conductive layer 240.
An anti-reflection layer ARL may be disposed on the input sensor ISP. The anti-reflection layer ARL may include a division layer 310, a color filter 320, and a planarization layer 330.
A material constituting the division layer 310 is not particularly limited as long as being a material that absorbs light. The division layer 310 may include a plurality of patterns which are spaced apart from each other, without being limited thereto. The patterns of the division layer 310 may have a black color, and in an embodiment, the division layer 310 may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include a carbon black, a metal such as chrome, or an oxide thereof.
Patterns of the division layer 310 may cover the second conductive layer 240 of the input sensor ISP. The division layer 310 may prevent external light from being reflected by the second conductive layer 240. An opening portion 310-OP may be defined by patterns of the division layer 310, where the solid portions (e.g., patterns) and the opening portion 310-OP together define the division layer 310. The opening portion 310-OP may overlap the anode AE. The color filter 320 may overlap the opening portion 310-OP. The color filter 320 may be in contact with the division layer 310.
The planarization layer 330 may cover the division layer 310 and the color filter 320. The planarization layer 330 may include an organic matter, and an upper surface of the planarization layer 330 may be provided with a flat surface. In an embodiment of the invention, the planarization layer 330 may be omitted.
Referring to
The sixth insulating layer 60, the seventh insulating layer 70, and the pixel defining layer PDL (together as a stacked structure) which terminate in the non-display region DP-NDA, expose the fifth insulating layer 50 in the non-display region DP-NDA, to outside the stacked structure. The inorganic encapsulation layers 141 and 143 of the encapsulation layer 140 may be in contact with the exposed portion of the fifth insulating layer 50. As being in contact, elements may form an interface therebetween, without being limited thereto. It is illustrated that the first and second insulating layers 210 and 230 of the input sensor ISP, and the planarization layer 330 of the anti-reflection layer ARL, also entirely overlap the display region DP-DA and the non-display region DP-NDA. However, an embodiment of the invention is not limited thereto.
The data line DL may include a plurality of parts disposed on different layers. The plurality of parts may include conductive patterns in different layers from each other. As illustrated in
Since the second part DL-P2 is formed through the same process as the gate GT1 of the silicon transistor S-TFT, such as to be in a same layer as the gate GT1, the second part DL-P2 may have the same material and the same stacked structure as the gate GT1. The first part DL-P1 is disposed in the display region DP-DA, and in the non-display region DP-NDA, the first part DL-P1 is connected to the second part DL-P2 through a contact hole passing through the second to sixth insulating layers 20 to 60 as a collective insulating layer. In an embodiment of the invention, the data line DL may include only a part disposed on any one insulating layer, and is not particularly limited.
An end portion EP of the second part DL-P2 may overlap the pad region PA. The end portion EP of the second part DL-P2 may be defined as a pad portion of the data line DL or of the display panel 100. The display panel 100 may constitute the display panel DP illustrated in
An open region 110-OP (hereinafter referred to as a second open region), which corresponds to the end portion EP of the second part DL-P2, is defined in the base layer 110. The second open region 110-OP having the same size (e.g., planar size or planar area) as the first open region PF-OP is illustrated as an example, but an embodiment of the invention is not limited thereto. One open region among the first open region PF-OP and the second open region 110-OP may be larger than the other. For example, the first open region PF-OP may extend to the corner and/or end surface of the base layer 110 to define a notch in the lower film PF on a plane. In an embodiment of the invention, when the lower film PF has a substantially smaller area than the base layer 110 to expose the pad region PA, a hatched portion of the lower film PF, which is illustrated in
An open region 10-OP (hereinafter referred to as a third open region), which corresponds to the second open region 110-OP, is defined also in the insulating layers 10br, 10bf and 10 disposed between the end portion EP of the second part DL-P2 and the lower film PF. The second open region 110-OP and the third open region 10-OP may be formed through the same process, for example, a laser irradiation process. The first open region PF-OP, the second open region 110-OP, and the third open region 10-OP may be aligned with each other to define an open region which exposes the end portion EP to outside the display module DM.
The end portion EP of the second part DL-P2 may be electrically connected to a flexible circuit board FCB, such as through a bonding process. The end portion EP of the second part DL-P2 may be electrically connected to a signal line F-SL of the flexible circuit board FCB, through an anisotropic conductive film ACF.
According to an embodiment of the invention, the pad region PA may be disposed in a region overlapping the pixel defining layer PDL unlike what is illustrated in
The pad region PA may be further moved in the right direction to overlap the display region DP-DA. The pad region PA may overlap, in common, the non-display region DP-NDA and the display region DP-DA, or may overlap the display region DP-DA adjacent to the non-display region DP-NDA, for example, a region overlapping the oxide transistor O-TFT.
Referring to
The end side surface ED-P of the end portion EP may be in contact with the resin structure LS illustrated in
Referring to
The sub-base layer 110-S may include the same material as the base layer 110, for example, polyimide. The sub-base layer 110-S may have a smaller thickness than the base layer 110.
The at least one inorganic layer 110-SL may be the barrier layer 10br and/or the buffer layer 10bf, described with reference to
Referring to
Referring to
The sixth insulating layer 60 and the seventh insulating layer 70, which overlap the pad region PA, may support the pad region PA during a bonding process in
As illustrated in
In a state where the display module DM and the lower film PF are attached, the preliminary display device DD-P is separated from a mother substrate (not shown), where the mother substrate may include plural of the preliminary display device DD-P, without being limited thereto. The upper film UF and the window WM are attached, in sequence, to an upper side of the display module DM having the lower film PF attached thereto. Thereafter, the cover panel CP is attached to a lower side of the lower film PF, to provide the preliminary display device DD-P.
As illustrated in
As illustrated in
The process for bonding the flexible circuit board FCB and the anisotropic conductive film ACF, to the display module DM, using the bonding head HD is described with reference to
As illustrated in
Unlike what is illustrated in
Referring to
A first adhesive layer AL1 bonds a window WM to a display module DM. The first adhesive layer AL1 does not overlap the pad region PA.
As illustrated in
The first resin structure LS1 is disposed between the window WM and the display module DM to bond the window WM and the pad region PA of the display module DM, to each other. With respect to the pad region PA, the first resin structure LS1 serves as the upper film UF described with reference to
A second resin structure LS2 corresponds to the resin structure LS described with reference to
As illustrated in
As illustrated in
As illustrated in
As illustrated in
As illustrated in
According to an embodiment of the invention, the flexible circuit board FCB is coupled onto the rear surface of the display panel DP. Since the non-display region DP-NDA of the display panel DP is not bent or deformed during coupling of the flexible circuit board FCB to the display module DM, a defect occurring in a bending region of the non-display region DP-NDA may be reduced or effectively prevented. In addition, since the non-display region DP-NDA of the display panel DP is not bent or deformed during coupling of the flexible circuit board FCB to the display module DM, the planar area of the bezel region BA of the window WM, for covering the non-display region DP-NDA of the display panel DP, may be reduced.
The upper film UF or the resin structure which corresponds to the pad region PA, supports the pad region PA of the display panel DP in the process for bonding the display panel DP and the flexible circuit board FCB to each other. Thus, the reliability of bonding the display panel DP and the flexible circuit board FCB may be improved.
The resin structure as the first resin structure LS1 or the second resin structure LS2 together with the first resin structure LS1, may fix the flexible circuit board FCB to the display module DM and protect the pad region PA of the display panel DP. The resin structure may block moisture from being penetrated into the pad region PA of the display panel DP, especially to layers of the display device DD (or electronic device ED) which have end surfaces exposed to outside.
Although the embodiments of the invention have been described, it is understood that the invention should not be limited to these embodiments but various changes and modifications can be made by one ordinary skilled in the art within the spirit and scope of the invention as hereinafter claimed. Therefore, the technical scope of the invention is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0044749 | Apr 2022 | KR | national |
