Patent Application
20240355365
This disclosure relates to memory and, in particular, to static random access memory (SRAM) employing a metal capacitor to assist read and/or write accesses to memory cells in the SRAM. Still more particularly, the present disclosure relates to a metal boost capacitor that may be utilized to selectively and concurrently provide a voltage boost to one or more different assist circuits to assist accesses to memory cells in the SRAM.
SRAM is often employed in embedded applications to provide high performance memory within an integrated circuit. For example, SRAM can be utilized to implement critical path storage, such as cache memory or an address translation structure, in a high performance processor. In such embedded applications, it is desirable to implement a relatively low upper supply voltage (VDD) for the SRAM in order to reduce power dissipation and heat. However, to maintain high performance for read and write operations, it is also desirable to utilize various assist circuits to temporarily boost one or more line voltages above upper supply voltage VDD or below a lower supply voltage VSS (e.g., ground voltage).
In some prior art SRAMs, a boost capacitor is utilized within an assist circuit to boost a line voltage above upper supply voltage VDD or below lower supply voltage VSS. One known technique of implementing such a boost capacitor is by depositing a series of parallel metal lines over the SRAM cells. In such implementations, a first set of the metal lines (or “wires”) serve as a first “plate” of the capacitor, a disjoint second set of the metal lines serve as a second “plate” of the capacitor, and the desired capacitance is generated by the capacitive coupling between the first and second sets of metal lines. Although the use of a metal capacitor to provide read/write assist is convenient, decreasing minimum features sizes have reduced the chip area available for the metal lines forming a boost capacitor. Consequently, it has proved difficult to as a matter of floor planning to allocate adequate chip area for the respective boost capacitor of each of the various assist circuits of the SRAM.
In view of the foregoing, the present application recognizes that it would be useful and desirable to provide a circuit and method that enable a common boost capacitor to be selectively and concurrently provide a voltage boost to one or multiple assist circuits in a SRAM.
In one or more embodiments, an integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) cell array and a first assist circuit and a differently configured second assist circuit. The first assist circuit is configured to apply a voltage boost to an access line utilized to access the SRAM cell array, and the second assist circuit is configured to apply a voltage boost to a voltage supply rail of the SRAM cell array. A common boost capacitor is coupled to selectively and concurrently provide a voltage boost to both the access line and the power rail via the first and second assist circuits, respectively.
With reference to the figures and with particular reference to
In the depicted embodiment, each SRAM 104 includes a plurality of independently controllable SRAM macros 110. In some implementations, processor 100 is configured to initially place a first subset of the SRAM macros 110 into service and to reserve a second subset of SRAM macros 110 as spare(s) that can be substituted for a failing or failed SRAM macro 110. Those skilled in the art will appreciate that in some embodiments, one or more of SRAMs 104 and/or SRAM macros 110 may be implemented within processor 100, but not within one of cores 102. Further, in some embodiments, one or more SRAM macros 110 may form a shared spare pool from which processor 100 can automatically allocate storage to any one of multiple cores 102, for example, in place of a failing or failed SRAM macro 110.
With reference now to
SRAM macro 110 includes a macro controller 210 having a first input that receives a reference clock signal 212 and a second input that that receives read/write access commands 214, each specifying a target address. In response to these inputs, macro controller 210 orchestrates read and write accesses to the relevant memory cells 202 within SRAM cell array 200. In some embodiments, these accesses include, in addition to reads and writes of a full row of memory cells 202, a partial write to only a subset of the memory cells 202 comprising a row of memory cells 202. Macro controller 210 is coupled to an address decoder 216, to which macro controller 210 forwards the target address of each read or write command. Address decoder 216, which includes a wordline driver (WLD) 218 for each wordline 204, decodes the target address to identify a corresponding wordline 204. The wordline driver 218 for the identified wordline 204 then asserts its corresponding wordline 204 to access memory cells 202 in the associated row of SRAM cell array 200. For a write command, macro controller 210 also controls write circuitry 220 to apply write data received in conjunction with the write command to the relevant bit lines 206, thus updating the accessed memory cells 202. For a read command, assertion of the selected wordline 204 causes the bits stored in the memory cells 202 coupled to that wordline 204 to be read out onto bitlines 206, detected by sense amplifiers 222, and buffered in output buffer 224. The output data are passed to an error correcting code (ECC) circuit 226, which detects, and if possible, corrects, errors in the output data. The corrected output data are returned to a requestor as read data. ECC circuit 226 additionally reports, via signal line 228, any correctable errors (CEs) and uncorrectable errors (UEs) detected in the output data to macro controller 210. For CEs, ECC circuit 226 may optionally provide the corrected data to write circuitry 220 as write data in order to enable the corrected data to be written back into SRAM cell array 200.
In accordance with the disclosed inventions, SRAM macro 110 includes multiple assist circuits, where each such assist circuit is configured and coupled to selectively and temporarily boost a voltage of one or more conductive lines within SRAM cell array 200 either positively (a positive boost) or negatively (a negative boost) during a read or write access. As noted above, such assist circuits are conventionally employed with SRAMs to retain a desired level of performance while reducing baseline power dissipation and heat. For example, in some embodiments, SRAM macro 110 may employ such an assist circuit with wordline drivers 218 to enable wordline drivers 218 to boost a voltage pulse applied to wordlines 204 above upper supply voltage VDD during read and/or write accesses to SRAM cell array 200. In some embodiments, SRAM macro 110 may alternatively or additionally include such an assist circuit within cell supply connections 208 in order to temporarily apply a positive boost to the voltage of the upper cell power supply rail of memory cells 202 and/or to temporarily apply a negative boost to the voltage on the lower cell power supply rail of memory cells 202. In some embodiments, SRAM macro 110 may alternatively or additionally include such assist circuits within write circuitry 220 to apply a boost (usually negative) to the precharge voltage applied to bitlines 206.
With reference now to
In contrast to prior art circuits in which each assist circuit has its own respective boost capacitor, in the embodiment of
Referring now to
In the example of
In the embodiment of
During an idle period between accesses to SRAM cell array 200, macro controller 210 sets the VCELL_Boost_CTL signal logic high (e.g., 0b1), causing PMOS transistor 406 to be turned on to charge node 314 connected to second plate 310 to upper supply voltage VDD. In addition, macro controller 210 sets the Idle_PC signal logic high (e.g., 0b1), causing first plate 308 to be set to the opposite voltage state from second plate 310 (i.e., logic low). When a boost operation is active (e.g., during an access to SRAM cell array 200), macro controller 210 deasserts (e.g., switches to 0b0) the VCELL_Boost_CTL signal and continues to assert the Idle_PC signal. As a result, the output of NAND gate 408 changes from logic high to logic low, which switches the voltage on first plate 308 from the logic low state to the logic high state to provide a coupling action to second plate 310 and thus positively boost the voltage of second plate 310 and node 314. Deasserting the VCELL_Boost_CTL signal also disconnects second plate 310 from upper supply voltage VDD, enabling the voltage of second plate 310 to float in order to allow the coupling effect of first plate 308 switching states to impact the voltage state of second plate 310.
The boost circuit arrangement of
The boost circuit arrangement of
Referring now to
The process of
Similarly, if macro controller 210 asserts the active-low WL_BOOST_SEL signal for a given wordline 204, the associated wordline assist circuit 430 applies the voltage present on common boost capacitor 306 to the wordline 204, as shown at reference numeral 604 of
The implementation of a common boost capacitor for multiple assist circuits has several advantages. The use of a common boost capacitor increases writability by supplying a wordline boost during write operations and provides stability for read operations. In cases in which only a partial row of SRAM cells is written, application of a voltage boost to the wordline improves writability for the written memory cells and stability for the non-written memory cells. In addition, during read operations, performance (latency) is improved by application of a voltage boost to both the accessed wordline and upper cell supply voltage rails of the accessed memory cells. The use of a common boost capacitor for multiple different types of assist circuits provides better control over the boost levels and improved synchronization the timing of application of the boost voltages to the different conductive lines. Further, the use of a common boost capacitor for multiple different types of assist circuits reduces the wire resources and chip area required to implement a boost capacitor and improves integrated circuit yield by reducing the probability of a short circuit due to high metal density.
The present application additionally appreciates that writability of SRAM memory cells can also be improved by applying a negative boost voltage to bitlines of the SRAM cells to be written, where the negative boost can be selectively applied either alone or in combination with a positive wordline boost as previously described.
In the embodiment of
During an idle period between accesses to SRAM cell array 200, macro controller 210 sets the BL_Boost_CTL signal logic low (e.g., 0b0), causing NMOS transistor 706 to be turned on to set node 714 connected to second plate 710 to lower supply voltage VSS. In addition, macro controller 210 sets the BL_Idle_PC signal logic low (e.g., 0b0), causing first plate 708 to be set to the opposite voltage state from second plate 710 (i.e., logic high). When a boost operation is active (e.g., during a write access to SRAM cell array 200), macro controller 210 selectively asserts (e.g., switches to 0b1) the BL_Boost_CTL signal and continues to maintain the BL_Idle_PC signal logic low. As a result, the output of NOR gate 712 changes from logic low to logic high, which switches the voltage on first plate 308 from the logic high state to the logic low state. This voltage change provides a coupling action to second plate 710 and thus negatively boosts the voltage of second plate 710 and node 714 below VSS. Asserting the BL_Boost_CTL signal also disconnects second plate 710 from upper supply voltage VSS, enabling the voltage of second plate 710 to float in order to allow the coupling effect of first plate 708 switching states to impact the voltage state of second plate 710.
The negative boost circuit arrangement of
In practice, the gates of NMOS transistors 722 and 726 can driven by the same control signal, for example, BS_WR<0>, and the gates of NMOS transistors 724 and 728 can be controlled by the true and complement of the relevant bit of write data. With this arrangement, during a write operation to the illustrated column of SRAM cell array 202, macro controller 210 asserts high BS_WR<0> to open both of NMOS transistors 722 and 726. Depending on which of NMOS transistors 724 or 728 is opened by the write data bit, a “0” is written to BLT or BLC, respectively. With this arrangement, BS_WR<1> could then be connected to a neighboring memory cell to select whether or not to write to a different column's bit lines 206. It should be noted that with the disclosed boost circuit arrangements, macro controller 210 can selectively provide a positive voltage boost to a wordline 204 and/or a positive voltage boost to an upper cell supply voltage rail 400 and/or a negative voltage boost to a bitline 206. Further, macro controller 210 can apply multiple of these voltage boosts concurrently.
Referring now to
Referring now to
Design flow 900 may vary depending on the type of representation being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component or from a design flow 900 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
Design process 910 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or logic structures shown herein to generate a netlist 980 which may contain design structures such as design structure 920. Netlist 980 may comprise, for example, compiled or otherwise processed data structures representing a list of wires, discrete components, logic gates, control circuits, I/O devices, models, etc. that describes the connections to other elements and circuits in an integrated circuit design. Netlist 980 may be synthesized using an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the device. As with other design structure types described herein, netlist 980 may be recorded on a machine-readable storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, a compact flash, or other flash memory. Additionally, or in the alternative, the medium may be a system or cache memory, or buffer space.
Design process 910 may include hardware and software modules for processing a variety of input data structure types including netlist 980. Such data structure types may reside, for example, within library elements 930 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 10 nm, 20 nm, 30 nm, etc.). The data structure types may further include design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 which may include input test patterns, output test results, and other testing information. Design process 910 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc. One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 910 without deviating from the scope and spirit of the invention. Design process 910 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 910 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 920 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 990. Design structure 990 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g., information stored in an IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Similar to design structure 920, design structure 990 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown herein. In one embodiment, design structure 990 may comprise a compiled, executable HDL simulation model that functionally simulates one or more of the devices shown herein.
Design structure 990 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g., information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 990 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown herein. Design structure 990 may then proceed to a stage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
As has been described, in at least one embodiment, an integrated circuit includes a semiconductor substrate and integrated circuitry on the semiconductor substrate. The integrated circuitry includes a static random access memory (SRAM) cell array and a first assist circuit and a differently configured second assist circuit. The first assist circuit is configured to apply a voltage boost to an access line utilized to access the SRAM cell array, and the second assist circuit is configured to apply a voltage boost to a voltage supply rail of the SRAM cell array. A common boost capacitor is coupled to selectively and concurrently provide a voltage boost to both the access line and the power rail via the first and second assist circuits, respectively.
While various embodiments have been particularly shown and described, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims and these alternate implementations all fall within the scope of the appended claims. For example, although aspects have been described with respect to a computer system executing program code that directs the functions of the present invention, it should be understood that present invention may alternatively be implemented as a program product including a computer-readable storage device storing program code that can be processed by a processor of a data processing system to cause the data processing system to perform the described functions. The computer-readable storage device can include volatile or non-volatile memory, an optical or magnetic disk, or the like, but excludes non-statutory subject matter, such as propagating signals per se, transmission media per se, and forms of energy per se.
As an example, the program product may include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, or otherwise functionally equivalent representation (including a simulation model) of hardware components, circuits, devices, or systems disclosed herein. Such data and/or instructions may include hardware-description language (HDL) design entities or other data structures conforming to and/or compatible with lower-level HDL design languages such as Verilog and VHDL, and/or higher level design languages such as C or C++. Furthermore, the data and/or instructions may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures).
The figures described herein and the written description of specific structures and functions are not presented to limit the scope of what Applicants have invented or the scope of the appended claims. Rather, the figures and written description are provided to teach any person skilled in the art to make and use the inventions for which patent protection is sought. Those skilled in the art will appreciate that not all features of a commercial embodiment of the inventions are described or shown for the sake of clarity and understanding. Persons of skill in this art will also appreciate that the development of an actual commercial embodiment incorporating aspects of the present inventions will require numerous implementation-specific decisions to achieve the developer's ultimate goal for the commercial embodiment. Such implementation-specific decisions may include, and likely are not limited to, compliance with system-related, business-related, government-related and other constraints, which may vary by specific implementation, location and from time to time. While a developer's efforts might be complex and time-consuming in an absolute sense, such efforts would be, nevertheless, a routine undertaking for those of skill in this art having benefit of this disclosure. It must be understood that the inventions disclosed and taught herein are susceptible to numerous and various modifications and alternative forms. Lastly, the use of a singular term, such as, but not limited to, “a” is not intended as limiting of the number of items.
