Number | Name | Date | Kind |
---|---|---|---|
4508978 | Reddy | Apr 1985 | |
4639622 | Goodwin et al. | Jan 1987 | |
4649523 | Holder, Jr. et al. | Mar 1987 | |
4678941 | Chao et al. | Jul 1987 | |
4688063 | Lu et al. | Aug 1987 | |
4704706 | Nakano | Nov 1987 | |
4731552 | Miyamoto | Mar 1988 | |
4789648 | Chow et al. | Dec 1988 | |
4801988 | Kenney | Jan 1989 | |
4814647 | Tran | Mar 1989 | |
4831592 | Nakani | May 1989 | |
4896297 | Miyatake et al. | Jan 1990 | |
4905314 | Kato et al. | Feb 1990 | |
4906056 | Taniguchi | Mar 1990 | |
4944836 | Beyer et al. | Jul 1990 | |
4954731 | Dhong et al. | Sep 1990 | |
4967399 | Kuwabara | Oct 1990 | |
5010259 | Inoue et al. | Apr 1991 | |
5038325 | Douglas et al. | Aug 1991 | |
5059816 | Kobatake | Oct 1991 | |
5159215 | Murotani | Oct 1992 |
Entry |
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R. Scheuerlein et al., "Offset Word Line Architecture for Scaling DRAMs to the Gigabit Level," Center for Integrated Systems, 1987 Symposium on VLSI Circuits, Session VI-4, pp. 81-82. |