The present invention relates to a booster circuit, such as can be used, in particular, in integrated circuits in clocked dynamic circuit technology (for example DDCVS circuit technology) for boosting signals.
“Domino Differential Cascode Voltage Switch” circuit technology (DDCVS circuit technology) is suitable as clocked dynamic circuit technology for implementing complex basic functions, such as, for example, a partial product former, summation former, carry former and an AND-OR-XOR function. In the process, these complex basic functions are generally implemented as single-stage cells in each case.
In the example shown, the NMOS network 61, as indicated above, forms a function of a single-stage partial product former (ppb) for a Booth multiplier. In this instance, the input signals 11 to 20 are linked to the output signal 3 according to a configuration of the transistors 35 to 46 shown in
ppb=((x1·z)+(x0·z2))·s—n+(x1
In this instance, the following relationships for the reference numerals in
x0 13, x0
wherein a suffix “_n” stands for an inversion in each case, i.e. x0
The more complex the function to be produced, the more transistors are generally connected in series in the NMOS network 61. In the example shown in
In order for the circuit section 1 shown in
When the output load of a circuit section 1 of this type is large, the circuit section 1 has to have a high basic driver strength, in order to be able to reload the load within a predetermined time. Because the NMOS network 61 of any circuit section 1 generally has many transistors (twelve in the example) and each of these transistors has to have a multiple channel width (factor four in this example), in order to ensure the required driver capacity, the area requirement of a circuit section of this type in the layout of a microelectronic circuit is very large and increases according to a required driver capacity.
In order to increase the driver capacity of the circuit section 1, apart from the above-mentioned possibility of increasing the channel width of transistors, there is the possibility of inserting a driver cell 101 at the output of the circuit section 1, as shown in
In order to achieve the same driver capacity as in the circuit variant shown in
The feeding of the clock signal 105 to the driver cell 101, is in itself a drawback, as, for example, in comparison to the circuit variant shown in
For this reason, an object of the present invention is to provide a circuit variant, which allows large loads to be driven, but in the process optimises the running time and/or the area requirement in comparison to known circuit variants.
A further object of the present invention is to provide a circuit variant for driving large loads, wherein, in comparison to known circuit variants with constant running time and area requirement, the dissipated power is reduced.
These objects are achieved by a booster circuit according to claim 1. The dependent claims define preferred and advantageous embodiments of the invention.
The booster circuit has a first signal connection, which is to be connected to a signal line conducting a first signal, and a second signal connection, which is to be connected to a signal line conducting a second signal. In the process, the booster circuit is designed in such a way that it amplifies a voltage difference between the first signal and the second signal at the first and second signal line in that it draws the first signal to a first potential which differs from a potential of the first signal and/or draws the second signal to a second potential which differs from a potential of the second signal.
While the voltage difference between the first and the second signal at the first and second signal line is amplified, and, for example, a driver cell does not amplify the two signals, in that the two signals run through this driver cell where they are amplified, as is conventional in the prior art (see, for example,
The booster circuit can amplify this voltage difference between the first signal and the second signal in that it draws the second signal to a first potential (for example a supply potential VSS) when a voltage difference between the first signal and this first potential is greater than a voltage difference between the second signal and this first potential. Accordingly, the booster circuit can amplify the voltage difference, in that it draws the first signal to the first potential when a voltage difference between the second signal and the first potential is greater than a voltage difference between the first signal and the first potential. This assumes, however, that the first potential is either at least as high as both the potential of the first signal and the potential of the second signal or at least as low as both the potential of the first signal and the potential of the second signal. In other words, the first potential should not lie “between” the potentials of the two signals, which is automatically fulfilled if, as already noted above, the first potential is a supply potential.
In accordance with the invention, the signal (either the first or the second signal) is therefore drawn to the first potential, the potential of which lies closer to this first potential. A circuit arrangement of this type is, in particular, advantageous when, on the one hand, the first signal is inverted with respect to the second signal, and, on the other hand, the first potential is the potential at which the first or the second signal would charge or discharge even without a booster circuit.
In the process, the first or the second signal is preferably only drawn to the first potential when a clock pulse, which is fed to the booster circuit, is applied.
As the booster circuit only draws the first or the second signal to the first potential when a clock pulse is applied, the booster circuit does not change the potential of the first or second signal when no clock pulse is applied. This is advantageous when the two signals are output signals of a clocked circuit arrangement connected to the booster circuit. In this constellation, the two signals, if no clock pulse is applied, have an undefined or irrelevant value (potential), so an amplification of the voltage difference between the two signals during a phase in which the clock pulse is not applied, would not be sensible or would be disadvantageous.
In addition, the booster circuit can be designed in such a way that it draws (precharges) the first and/or the second signal to a second potential (a supply potential) if a further clock signal is not applied. In the process, the further clock signal may correspond to the clock pulse described above. In a similar manner to the case with the first potential, this again assumes, however, that the second potential is either at least as high as both the potential of the first signal and also the potential of the second signal or is at least as low as both the potential of the first signal and the potential of the second signal, which is fulfilled, for example, when the second potential is the supply potential VDD.
Precharging to the second potential is advantageous, in particular when this second potential corresponds to a potential to which the first or the second signal were charged or discharged even without the presence of the booster circuit when the clock pulse is applied. Moreover, the precharging to the second potential is advantageous if the booster circuit cooperates with a circuit arrangement which also precharges the two signals to the second potential.
However, the booster circuit may also be designed in such a way that it compensates a voltage difference between the first and the second signal, when a further clock pulse, which may correspond to the previously described clock pulse, is not applied.
Compensating the voltage difference between the first and the second signal is advantageous, in particular, when the booster circuit cooperates with a circuit arrangement which precharges the two signals, for example, to the second potential. Due to compensation of the voltage difference, which can be implemented in that the two signals are connected virtually without resistance via a circuit unit (for example a transistor) when the previously described further clock pulse is not applied, the charging of the two signals is assisted by the mentioned circuit arrangement.
In addition, the booster circuit can draw the second signal to the second potential when a voltage difference between the first signal and the second potential is greater than a voltage difference between the second signal and the second potential, in order to draw the first signal to the second potential when a voltage difference between the second signal and the second potential is greater than a voltage difference between the first signal and the second potential. In a similar manner to that described above repeatedly, this again assumes, however, that the second potential is either at least as high as both the potential of the first signal and the potential of the second signal or at least as low as both the potential of the first signal and the potential of the second signal, which is fulfilled, for example when the second potential is the supply potential VDD.
In a similar manner to that described for the first potential, in accordance with the invention, the signal (either the first or the second signal) is drawn to the second potential, the potential of which lies closer to this second potential. A circuit arrangement of this type is advantageous, in particular, when, on the one hand, the first signal is inverted with respect to the second signal, and on the other hand, the second potential is the potential to which the first or the second signal is charged or discharged even without a booster circuit.
It should be pointed out that the previously described features with respect to the amplification of a voltage difference by drawing to the first potential, and with respect to the amplification of a voltage difference, by drawing to the second potential are independent of one another in principle and contribute separately in each case to achieving said objects.
As already mentioned above in the description of some advantages in accordance with the invention, the booster circuit may be connected to a circuit section from which a first and a second output signal can be picked up, in such a way that the first output signal is connected to the first signal and the second output signal is connected to the second signal of the booster circuit. In the process, at least one input signal can be fed to the circuit section, the circuit section determining the first output signal as a function of the at least one input signal and determining the second output signal inversely to the first output signal.
In the process, the circuit section may be designed in such a way that a clock signal (clock pulse) can be fed to it, and in that if the clock pulse is not applied, it draws the first and the second output signal to a second supply potential which corresponds to the second potential, and in that only if the clock pulse is applied, it determines the first output signal as a function of the at least one input signal. In the process, the clock signal of the circuit section may be equal to the clock signal of the booster circuit. Furthermore, both the circuit section and the booster circuit can be constructed with transistors.
In accordance with the invention, the transistors of the booster circuit may be designed in such a way that a driver capacity of a circuit arrangement consisting of the circuit section and the booster circuit can be selected virtually as desired, without the transistors of the circuit section being changed. This has the decisive advantage that the transistors of the circuit section can be designed to be small or space saving, without the driver capacity of the circuit arrangement being limited thereby. It is therefore possible for the circuit arrangement to drive large loads, without having to accept lengthening of the running time, in that only the booster circuit is set up or dimensioned accordingly.
In order for the circuit arrangement to be able to drive large loads, in accordance with the invention, the channel width of the transistors of the booster circuit can be extended according to the required driver capacity of the circuit arrangement. A further possibility of increasing the driver capacity of the circuit arrangement is to dynamically reduce the threshold voltage of the respectively connected transistors of the booster circuit, for example by substrate control.
The present invention is suitable, for example, for use in integrated circuits, which are constructed in clocked dynamic circuit technology, in particular the DDCVS circuit technology, in order to be used in high speed communication applications (line cards, network processors). Obviously, the invention is not limited, however, to this application area, but may, for example, also be used in circuits constructed with bipolar transistors or in non-microelectronic circuits.
The present invention will be described in more detail hereinafter with the aid of a preferred embodiment and with reference to the accompanying drawings, in which:
As FIGS. 1 to 3 have already been described above, further description is dispensed with here and reference is made to the above description.
In the process, the booster circuit 2 is designed in such a way that it amplifies the voltage difference between the output signals 3, 4. It will be shown hereinafter how this configuration appears in detail.
As the booster circuit 2 operates with the same clock signal 5 as the circuit section 1, no additional evaluation signal or clock signal is required. For this reason and as the output signals 3, 4 do not run through the booster circuit 2, the booster circuit 2 does not need any additional running time and does not impair the timing.
In the case of the conditions selected in one example, the area requirement of the transistors for the circuit section 1 and the booster circuit 2 in the circuit variant shown in
A further advantage of the circuit variant shown in
The construction of the booster circuit 2 shown in
During a precharging phase, an NMOS evaluation transistor 56 is switched off by the clock signal 5 (clock pulse 5 is not applied or the clock signal is at VSS). The first signal 3 and second signal 4 are precharged to a supply potential VDD via the connected circuit section 1. A PMOS transistor 52 assists this precharging, in that it ensures charging compensation between the first signal 3 and the second signal 4.
Shortly before the start of an evaluation phase, the two signals 3, 4 are therefore at VDD, which means that a PMOS transistor 51 and a PMOS transistor 53 are switched off and an NMOS transistor 54 and an NMOS transistor 55 are connected, as the gate connection of these four transistors 51, 53 to 55 is connected in each case to one of the two signals 3, 4. At the beginning of the evaluation phase (clock pulse 5 is applied or clock signal 5 is at VDD), the evaluation transistor 56 becomes conductive, so a first path, which is defined by the NMOS transistor 54 and the evaluation transistor 56 and connected to the first signal 3, and a second path, which is defined by the NMOS transistor 55 and the evaluation transistor 56 and connected to the second signal 4, also become conductive, so the two signals 3, 4 are (briefly) drawn in the direction VSS 7.
However, as the connected circuit section 1, at the beginning of the evaluation phase, begins to draw either the first 3 or the second signal 4 in the direction VSS, either the transistor 54, when the second signal 4 is drawn by the circuit section 1 in the direction VSS, or the transistor 55, if the first signal 3 is drawn by the circuit section 1 in the direction VSS is more limited than the respective other transistor 54; 55, as the gate connection of the transistor 54 is connected to the second signal 4 and the gate connection of the transistor 55 is connected to the first signal 3. Therefore, either the first path or the second path becomes a poorer conductor than the other. Depending on which path becomes the poorer conductor, one of the two signals 3; 4 is drawn less strongly in the direction VSS or, after the shortest time, not drawn at all in the direction VSS when the corresponding transistor 54; 55 is completely limited, while the respective other signal 4; 3 continues to be drawn to VSS as at the beginning of the evaluation phase until completely discharged.
Advantageously, the signal 4; 3 continues to be drawn to VSS by the booster circuit 2, which signal was drawn to VSS at the beginning of the evaluation phase by the circuit section 1. Advantageously, a small voltage difference, which was initially only brought about slowly by the circuit section 1, is therefore amplified between the two signals 3; 4.
According to the same plan, as in the case of the NMOS transistors 54, 55, the first signal 3 is connected to VDD via the PMOS transistor 51 and the second signal 4, via the PMOS transistor 53. In the process, the gate connection of the transistor 51 is connected to the second signal 4 and the gate connection of the transistor 53 to the first signal 3. As the two signals 3, 4, as described already, are at VDD shortly before the beginning of the evaluation phase, the two PMOS transistors 51, 53 are blocked, as already described above.
However, as at the start of the evaluation phase, the circuit section 1, in addition to the booster circuit 2, that, as described, draws the two signals 3, 4 in the direction VSS at the beginning of the evaluation phase, begins to draw one of the signals 3; 4 to VSS, one of the transistors 51; 53 becomes more conductive than the respective other 53; 51. In an advantageous manner, this is the transistor 51; 53 which is connected to the signal 3; 4 which is not also drawn in the direction VSS by the circuit section 1, but is left at or drawn to VDD by the circuit section 1. Therefore, advantageously, the signal 3; 4 which is left at or drawn to VDD by the circuit section 1, is now also drawn by the booster circuit 2 to VDD, whereby the voltage difference between the two signals 3, 4 initially only brought about by the circuit section 1 is further amplified.
In the steady state, the booster circuit 2 draws the signal 3; 4 to VSS, which is also drawn by the circuit section 1 to VSS, and draws the signal 4; 3 to VDD, which is also left at or drawn to VDD by the circuit section 1. Therefore one of the PMOS transistors 53; 51 is conductive, while the respective other PMOS transistor 51; 53 blocks. In the same way, one of the NMOS transistors 53; 54 is conductive, while the respective other NMOS transistor 55; 54 blocks. Advantageously, the PMOS transistor 53; 51, of which the signal 4; 3 connected to the drain connection is at VDD, is conductive. In the same way, the NMOS transistor 54; 55, to the drain connection of which the signal 3; 4 at VSS is connected, is conductive. Therefore the steady state is extremely stable.
It should be noted that the booster circuit 2 would also operate advantageously if the PMOS transistors 51, 53 were not present. Furthermore, the PMOS transistor 52 could also, or additionally, be dispensed with without losing the basic functionality of the booster circuit 2.
Furthermore, in addition to the PMOS transistor 52, a further PMOS transistor 57, 58 could be present which precharges either the first 3 or the second 4 signal to VDD 8 in the precharging phase. This further PMOS transistor 57, 58 could be connected with its drain connection either to the first 3 or the second 4 signal and with its source connection to VDD. So that the first 3 or second 4 signal is then only precharged to VDD by this further PMOS transistor 57, 58, when the booster circuit 2 is in the precharging phase, the gate connection of the further PMOS transistor 57, 58 is connected to the clock signal 5.
In a further embodiment, instead of the PMOS transistor 58 (or in addition to the PMOS transistor 52) two further PMOS transistors 57, 58 could be present to be able to precharge the two signals 3, 4 in the precharging phase to VDD even without a connected circuit section. In the process, the drain connection of the first further PMOS transistor 57 would be connected to the first signal 3 and the drain connection of the second further PMOS transistor 58 to the second signal 4. The source connection of both the first 57 and the second 58 further PMOS transistor would be connected to VDD. For the same reason as in the first embodiment with a further PMOS transistor, the gate connections of the two further PMOS transistors are connected to the clock signal 5, so that the two signals 3, 4 are only charged to VDD when the booster circuit 2 is in the precharging phase.
While the booster circuit 2 of the embodiment is constructed with NMOS and PMOS transistors, there are also embodiments of the booster circuit which are constructed with transistors which all have the same conductivity type (for example only NMOS transistors or only bipolar transistors). Furthermore, embodiments are conceivable, in which the conductivity types of the transistors are distributed differently than in the embodiments described above in detail. For example, certain PMOS transistors 51 to 53, 57, 58 could also be designed as NMOS transistors, while certain NMOS transistors 54 to 56 could also be designed as PMOS transistors, wherein, in these cases, in certain circumstances, a further clock signal is required which is preferably inverted with respect to the available clock signal 5.
The circuit variants shown in FIGS. 2 to 4 will now be examined in more detail with respect to their running time with the results of a circuit simulation.
In this instance, the following prerequisites apply. The loads to be driven by each circuit variant and which are shown schematically in FIGS. 2 to 4 by a capacitor in each case, are the same. The transistor widths of the circuit variant shown in
b shows the course over time of the clock signals 5, 105 required for the three circuit variants. The clock signal, not shown, is used here in the simulation to trigger the periphery and has no influence on the interconnections.
a shows the course over time of the output signals 3, 3′, 103 of the three circuit variants, these being loaded respectively with the clock signals 5, 105 shown in
To summarise, it can be stated with respect to the running times, that the circuit variants of
A comparison of the area requirement of the circuit variants already described above shows that the two circuit variants of
The use of the booster circuit 2 therefore leads to the smallest area requirement and simultaneously to the shortest running time.
Number | Date | Country | Kind |
---|---|---|---|
130 50 337.4 | Oct 2003 | DE | national |