Booster circuit

Abstract

A booster circuit including a precharge capacitor (C.sub.2), a precharge driver circuit (20) having a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q.sub.21) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q.sub.1) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode.The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a booster circuit. More particularly, it relates to a booster circuit in a semiconductor memory device.

2. Description of the Related Arts

When the memory capacity of a dynamic random access memory (D-RAM) is increased, a voltage of a word line must be boosted above a voltage V.sub.CC of a power source at a high speed, since memory cells connected to the word line increase, and thus increase a capacitance of the word line connected thereto. In addition, in a stacked-capacitor type RAM, the capacitance of the word line is greatly increased. On the other hand, the boosting of the word line voltage will contribute to an improvement of the resistance against a soft error.

Booster circuits have been applied to DRAM devices having a large number of memory cells, for example 256 Kbits or more. The boosting of the voltage is realized by providing a capacitor having a capacitance which may be several times that of the capacitance of the word line connected thereto. A DRAM of 256 Kbits has 1024 memory cells along one word line, but a DRAM of 1 Mbits has 2048, accordingly, in the 1 Mbits DRAM, the capacitance connected to the word line is increased by as much as twice that of the 256 Kbits DRAM. This means that, for boosting, a large capacitance of the above capacitor is required in the DRAM devices having a large number of memory cells. Acordingly, it would seem that these devices suffer from the disadvantages of a low integration of the DRAM device due to the capacitor used to provide the above capacitance having a large area, thus preventing a high integration, and a low speed response for fully changing the voltage in the capacitor in question.

The defects of the prior arts will be described later in detail with reference to the drawings.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a booster circuit having a small size capacitor for boosting and a low power consumption and high speed operation.

Another object of the present invention is to provide a booster circuit, preferably applicable to a semiconductor memory device, for boosting a voltage of a word line of the device and improving integration of the device.

According to the present invention, there is provided a booster circuit for producing a boosted output signal including: first and second power sources for supplying a power source voltage; a first driver circuit connected between the first and second power sources and including a first bootstrap circuit for receiving first and second signals having exclusive logic levels and producing a first output signal in response to the first and second signals; a precharge capacitor operatively connected to receive the first output signal from the first driver circuit, for producing a second output signal having a voltage level higher than the power source voltage in response to the first output signal, the precharge capacitor being precharged when the second signal is supplied; and a second driver circuit connected between the first and second power sources, receiving the first and second signals, and including a second bootstrap circuit for producing a third output signal in response to the first and second signals, and a first switching circuit having a terminal connected to receive the second output signal from the precharge capacitor, and an output terminal from outputting the boosted output signal having a voltage level higher than the power source voltage, the first switching circuit switching to transfer the second output signal to the output terminal to form the boosted output signal in response to the third output signal. The booster circuit further includes a second switching circuit connected between the first power source and the output terminal and operating in response to the first signal.

The second switching circuit outputs a voltage to the output terminal in response to the first signal in advance of the switching of the first switching circuit.

The booster circuit preferably is applicable to a semiconductor memory device, for boosting a voltage of a word line at a high speed and improving integration.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and features of the present invention will be described below in detail with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a prior art boosting circuit;

FIG. 2 is a circuit diagram of another prior art boosting circuit;

FIG. 3 is a circuit diagram of still another prior art boosting circuit;

FIG. 4 is a graph illustrating wave forms in the circuit in FIG. 3;

FIG. 5 is a circuit diagram of a boosting circuit of an embodiment in accordance with the present invention; and

FIG. 6 is a graph illustrating wave forms in the circuit in FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing preferred embodiments of the present invention, a description will be given of the prior arts for reference.

FIG. 1 is a circuit diagram of a prior art word line voltage booster circuit disclosed in "DENSHI GIGYUTSU (Electronics Engineering)" Vol. 23, No. 3, pp 31. The circuit in FIG. 1 consists of a word line signal generation circuit 80, a delay circuit 81, MOS transistors Q.sub.82, Q.sub.83, and Q.sub.84, and capacitors C.sub.85 and C.sub.86. The precharge capacitor C.sub.86 is provided to boost a voltage of the word line WL. When a word line voltage .phi..sub.WL is raised to V.sub.CC, the transistor Q.sub.82 is turned ON, precharging the capacitor C.sub.86 from the word line WL. A load connected to the word line WL is reduced to half. The capacitor C.sub.86 is precharged through the transistor Q.sub.84. When .phi..sub.D is raised to V.sub.CC, the transistor Q.sub.83 is turned ON, superimposing the voltage precharged in the capacitor C.sub.86 onto the voltage of V.sub.CC -V.sub.TH. V.sub.TH represents a threshold voltage of the transistor.

However, in the circuit of FIG. 1, the capacitor C.sub.85 having a capacitance less than the capacitor C.sub.86 is connected to the word line WL, in addition to capacitors of the memory cells. Accordingly, the reduction of the power consumption in and the speed up of the circuit are still limited.

FIG. 2 is a circuit diagram of another prior art word line voltage booster circuit disclosed in NIKKEI ELECTRONICS, Oct. 24, 1983, PP. 185. The circuit shown in FIG. 2 consists of MOS transistors Q.sub.91 and Q.sub.92, normal bootstrap buffers 93 and 94, and a precharge capacitor C.sub.95. A capacitor C.sub.L represents a capacitor of the memory cells as a load.

Since the precharge capacitor C.sub.95 is directly connected to the word line WL, a load of the transistor Q.sub.91 is increased, and the operating speed of the circuit is slow.

FIG. 3 shows still another prior art word line voltage booster circuit consisting of a first driver circuit 20', a second driver circuit 19', and a precharge capacitor C.sub.1 provided between these circuits 20' and 19'. The driver circuits 19' and 20' receive a clock signal .phi. and a reset signal RST from a timing circuit 21 which outputs the signals .phi. and RST in response to a row address select RAS signal. An output OT of the driver circuit 19 is supplied to a word line WL through a row decoder 22.

The driver circuit 19' consists of MOS transistors Q.sub.11 to Q.sub.22 and a bootstrap capacitor C.sub.19. The driver circuit 20' consists of MOS transistors Q.sub.51 through Q.sub.65, which are interconnected between the voltage sources V.sub.CC and V.sub.SS, and a bootstrap capacitor C.sub.59 and a capacitor C.sub.66. References N.sub.1 to N.sub.5 and N.sub.21 to N.sub.27 indicate nodes.

In FIG. 3, the capacitor C.sub.1 for precharging the voltage is provided between the node N.sub.26 and a source of the transistor Q.sub.64 connected to drains of the transistors Q.sub.18 and Q.sub.21. The precharge capacitor C.sub.1 is not directly connected to the word line, since it is cut off by the transistor Q.sub.21 in a reset mode. Accordingly, the circuit shown in FIG. 3 is beneficial to the problem of the circuit shown in FIG. 2. In addition, a capacitor corresponding to the capacitor C.sub.85 in FIG. 1 is not provided in the circuit shown in FIG. 3, and accordingly, the circuit shown in FIG. 3 is beneficial to the problems of the circuit shown in FIG. 1.

However, the circuit shown in FIG. 3 still suffers from disadvantages which will be described later.

The operation of the circuit in FIG. 3 will be described with reference to the various voltage wave forms in FIG. 4. At first, the reset signal RST, which is one of the input signals to the circuit 20', remains at the "H" level, and the signal .phi., which is another input to the circuit 20', remains at the "L" level. Thus, the transistor Q.sub.52 is kept ON, the transistor Q.sub.51 is kept OFF, the node N21 is kept "L", the transistor Q.sub.54 is kept OFF, and the transistor Q.sub.53 is kept ON. Therefore, the nodes N22 and N23 are kept "H", and accordingly, the gate capacitance of the transistor Q.sub.56 is charged up and the transistors Q.sub.60 and Q.sub.62 are kept ON. In addition, the node N24 is kept "L", and therefore the transistors Q.sub.58 and Q.sub.61 are kept OFF and the nodes N25 and N26 are kept "L". Furthermore, the node N27 is kept at the "HH" level, higher than the normal "H" level, due to the bootstrap effect according to the MOS capacitor C.sub.66 and the signal RST so that the transistor Q.sub.64 is kept fully ON. Therefore, the MOS capacitor C.sub.1 is charged up at the level of the voltage source V.sub.CC. Thus, at this stage, the output voltage V.sub.BS of the circuit 20' is kept at the V.sub.CC level.

Under the above-mentioned condition, when the signal RST falls, the potential VN.sub.27 of the node N27 falls to a level lower than the V.sub.CC level by the threshold voltage V.sub.TH of the transistor Q.sub.65, and the MOS capacitor C.sub.66 is charged up to this potential (V.sub.CC -V.sub.TH) so that any charge lost in the capacitor C.sub.66 while the bootstrap effect is being carried out is compensated. In addition, the output voltage V.sub.BS, which has been kept at the V.sub.CC level, is disconnected from the voltage source V.sub.CC because the transistor Q.sub.64 is turned OFF. This falling of the signal RST is effected before the rise of the signal .phi.. When the signal .phi. rises after the falling of the signal RST, the transistor Q.sub.51 is turned ON, the Q.sub.52 is kept OFF, the node N21 is turned to "H", the transistor Q.sub.54 is turned ON, the transistor Q.sub.53 is kept OFF, the node N22 is turned to "L", the transistors Q.sub. 56, Q.sub.60, Q.sub.62 are turned OFF, and the transistor Q.sub.57 is kept OFF. Therefore, the node N24 receiving the signal .phi. because the transistor Q.sub.56 is turned ON is turned to "H", the transistors Q.sub.58 and Q.sub.61 are turned ON, and the nodes N25 and N26 are turned to "H". Since the MOS capacitor C.sub.1 is charged up at the voltage source V.sub.CC as described above, the output voltage V.sub.BS is pushed above the voltage source V.sub.CC as shown in FIG. 4 when the mode N26 rises to the level of V.sub.CC due to the bootstrap effect of the MOS capacitor C.sub.59.

While in the circuit 19', when the signal .phi. rises, the transistor Q.sub.11 is turned ON, the transistor Q.sub.12 is turned OFF, the node N1 is turned to "H", the transistor Q.sub.14 is turned ON, and the transistor Q.sub.13 is kept OFF, and accordingly, the node N2 falls to the "L" level. Thus, the transistors Q.sub.20 and Q.sub.22 are turned OFF. Further, at the period between the signal .phi. rise and the node N3 charging, the transistor Q.sub.16 is kept ON, the transistor Q.sub.17 is kept OFF, and accordingly, the node N4 rises together with the signal .phi.. Accordingly, the transistors Q.sub.18 and Q.sub.21 are turned ON and are still more fully turned ON due to the bootstrap effect according to the MOS capacitor C.sub.19. Therefore, the levels of the node N5 and the output OT rise rapidly above the voltage source V.sub.CC following the output voltage V.sub.BS which is pushed up to the "HH" level, as shown in FIG. 4.

The capacitor C.sub.1 is charged up before the rising of the signal .phi., and the transistor Q.sub.64 in the charging circuit for the capacitor C.sub.1 is turned OFF so that the output V.sub.BS is pushed up through the capacitor C.sub.1 by the rising of the node N26 in response to the rising of the signal .phi., and the output voltage V.sub.BS is increased. Thus, the circuit of FIG. 3 has an advantage in that there is no delay in operation. Further, since the capacitor C.sub.1 is used as a voltage supply to the signal .phi. and is necessary for charging up the parasitic capacity accompanying the signal line of .phi., the capacity of the capacitor C.sub.1 should be relatatively large. Because the capacitor C.sub.1 has been charged up through the transistor Q.sub.64 preceding the rising of the signal .phi., the large capacity of the capacitor C.sub.1 does not cause a delay in operation. Accordingly, the access time of the memory device can be decreased by speeding up the rising transition of the output OT.

However, in the circuit shown in FIG. 3, a charge accumulated in the capacitor C.sub.1 is all output, and accordingly, if an even higher boosted voltage output to the word line is required in response to the increasing memory capacity, such as a 1 mega bit RAM device, an area forming the capacitor C.sub.1 having a capacitance which may be several times that of a load capacitance must be greatly increased. On the other hand, apparently the area forming the capacitor must be minimized due to the requirements of high integration and high density, etc. That is, the circuit in FIG. 3 encounters a problem of antonymity.

An embodiment of the present invention will now be described.

Referring to FIG. 5, a booster circuit includes a first driver circuit 20, a second driver circuit 19, a precharge capacitor C.sub.2, and an additional MOS transistor Q.sub.1.

The first driver circuit 20 consists of MOS transistors Q.sub.51 to Q.sub.54, Q.sub.56 to Q.sub.64, Q.sub.68 and Q.sub.69, and a boostrap capacitor C.sub.59. The first driver circuit 20 is similar to the driver circuit 20' in FIG. 3. The transistors Q.sub.68 and Q.sub.69 are provided instead of the transistor Q.sub.55 in FIG. 3, however, the principle of the operation of the driver circuit 20 is similar to that of the driver circuit 20' set forth above. In FIG. 5, the transistor Q.sub.65 and the capacitor C.sub.66 in FIG. 3 are added, and the reset signal supplied to a gate of the transistor Q.sub.64 in FIG. 5 may be regarded as a signal having the same nature as the node N.sub.27 in FIG. 3, set forth above.

Similarly, the driver circuit 19 has a same circuit construction as that of the driver circuit 19' in FIG. 3, except that MOS transistors Q.sub.25 and Q.sub.26 are provided instead of the transistor Q.sub.15 in FIG. 3.

The precharge capacitor C.sub.2 is provided in a same way as the capacitor C.sub.1 in FIG. 3, and thus the basic function of the capacitor C.sub.2 is identical to that of the capacitor C.sub.1.

The transistor Q.sub.1 is added between the V.sub.CC and an output terminal O.sub.X of the output OT. The transistor Q.sub.1 receives the clock signal .phi. at a gate thereof.

The operation of the circuit in FIG. 5 will be described with reference to FIG. 6.

When a RAS signal is not supplied to the timing circuit 21, in a reset mode, the timing circuit 21 outputs the reset signal RST having a high level, and the node N.sub.10 is then precharged, as set forth above. The duration of the reset mode is normally long enough to fully precharge the voltage in the precharge capacitor C.sub.2.

Upon receipt of the RAS signal, the timing circuit 21 causes a fall in the reset signal RST and a rise in the clock signal .phi., the reset signal RST and the clock signal being exclusive even if in a transition state.

By increasing the clock signal .phi., a voltage VN.sub.10 at the node N.sub.10 will be further raised to the voltage V.sub.CC, and a voltage VN.sub.4 at the node N.sub.4 is raised due to the boostrap effect of the capacitor C.sub.19. When the voltage VN.sub.4 reaches a predetermined level sufficient to fully turn ON the transistor Q.sub.21, the voltage VN.sub.10 at the node N.sub.10 is output to the output terminal O.sub.X. At the same time, the clock signal .phi. reaches the level V.sub.CC, and accordingly, the transistor Q.sub.1 is also fully turned ON. Consequently, the voltage V.sub.OT at the output terminal O.sub.X is superimposed onto the voltage of V.sub.CC through the transistor Q.sub.1, to the voltage from the node N.sub.10 through the transistor Q.sub.21.

The bootstrap circuit consisting of the capacitor C.sub.59 and the transistors Q.sub.58 and Q.sub.61 has a feature of fully discharging the charge stored in the precharge capacitor C.sub.2 to the output terminal O.sub.X through the transistor Q.sub.21 in an operation mode when the clock signal is enable. The bootstrap circuit including the capacitor C.sub.19 and the transistor Q.sub.18 has a feature of fully turning ON the transistor Q.sub.21 in the operation mode.

In the reset mode, the capacitor C.sub.2 is precharged, however, the capacitor C.sub.2 is cut off from the word line WL by the transistor Q.sub.21. The transistor Q.sub.1 is also turned OFF. Accordingly, the output of voltage V.sub.OT at the terminal O.sub.X is the voltage of V.sub.SS, which may be zero volt, in the reset mode. While, in the operation mode, the superimposed voltage of the precharged voltage of the precharge capacitor C.sub.2 and the voltage of V.sub.CC -V.sub.TH, which may be 4 volts, i.e., the boosted voltage, may appear at the output terminal O.sub.X and be output to the word line WL through the decoder 22.

Apparently, the driver circuit 20 functions as a precharge circuit for the capacitor C.sub.2, and the driver circuit 19 functions as a switching circuit for outputting or cutting the precharged voltage. The additional transistor Q.sub.1 functions as a switching circuit for superimposing the voltage V.sub.CC onto the precharge voltage.

When the capacitance of the precharge capacitor C.sub.2 in FIG. 5 is identical to that of the capacitor C.sub.1, apparently, the voltage V.sub.OT at the output terminal O.sub.X is higher than that of the voltage V.sub.OT ', shown by a dotted line in FIG. 6 and corresponding to a curve V.sub.OT ' in FIG. 4, by the voltage of V.sub.CC. In other words, the ciucuit in FIG. 5 may further boost the output voltage V.sub.OT higher than that boosted by the circuit in FIG. 3, by providing a single transistor Q.sub.1, when the capacitances of the capacitors C.sub.1 and C.sub.2 are identical. An area forming the transistor Q.sub.1 is a considerably smaller than that of the precharge capacitor. Accordingly, high boosting may be achieved without reducing the integration of the DRAM device.

To the contrary, when the boosting voltage equal to that in FIG. 3 is required, the capacitor C.sub.2 may be greatly reduced compared to the capacitor C.sub.1. This will contribute to the high integration of the DRAM device.

In the above embodiment, the booster circuit was described with reference to the RAM device, for boosting the word line of the device, however, the booster circuit may be also applied to other devices.

Many widely different embodiments of the present invention may be constructed without departing from the spirit and scope of the present invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification, except as defined in the appended claims.

Claims

1. A booster circuit for producing a boosted output signal comprising:

first and second power sources (V.sub.CC, V.sub.SS) for supplying a power source voltage;

a first driver circuit (20) connected between first and second power sources (V.sub.CC, V.sub.SS) and including a first bootstrap circuit (C.sub.59, Q.sub.58, Q.sub.61), for receiving first and second signals (.phi., RST) having exclusive logic levels and producing a first output signal in response to said first and second signals;

a precharge capacitor (C.sub.2) operatively connected to receive said first output signal from said first driver circuit, precharged to produce a second output signal when said second signal is supplied;

a second driver circuit (19) connected between said first and second power sources, receiving said first and second signals, and including a second bootstrap circuit (C.sub.19 and Q.sub.18) for producing a third output signal in response to said first and second signals, and a first switching circuit (Q.sub.21) having a terminal connected to receive said second output signal from said precharge capacitor, and an output terminal for outputting said boosted output signal having a voltage level higher than said power source voltage, said first switching circuit switching to transfer said second output signal to said output terminal to form said boosted output signal in response to said third output signal; and

a second switching circuit (Q.sub.1) connected between said first power source and said output terminal and operating in response to said first signal (.phi.),

said second switching circuit outputting a voltage to said output terminal in response to said first signal in advance of the switching of said first switching circuit.

2. A booster circuit according to claim 1, wherein said second switching circuit comprises a transistor (Q.sub.1).

3. A booster circuit according to claim 2, wherein said first switching circuit comprises a transistor (Q.sub.21).

4. A booster circuit according to claim 3, wherein said third output signal of said second bootstrap circuit has a voltage level high enough to fully turn ON said transistor of said first switching circuit.

5. A booster circuit according to claim 4, wherein said first output signal of said first bootstrap circuit has a voltage level high enough to fully output said voltage in said precharge capacitor to said output terminal through said transistor in said first switching circuit.

6. A booster circuit according to claim 5, wherein said voltage of said output terminal has a level approximately the same as the level of said second power source voltage when said second signal is supplied to said second driver circuit.

7. A booster circuit according to claim 6, wherein said second signal has an enable state longer than that of said first signal.

8. A dynamic metal insulation semiconductor memory device, according to claim 1, further comprising:

a timing circuit (21) generating said first and second signals in response to a memory access signal (RAS); and a word line (WL) operatively connected to said output terminal through a decoder (22), said output at said output terminal being supplied to said word line.