Bootstrapped high-speed output buffer

Abstract

An output buffer circuit comprises an input terminal for receiving an input signal, an output circuit coupled to a first node for outputting an output signal in response to a potential level appeared on the first node and a bootstrap circuit coupled between the first node and the input terminal. The bootstrap circuit comprises a delay circuit for delaying the input signal to provide a delayed input signal, a first transistor for receiving a signal inverted from the input signal, a second transistor coupled for receiving the delayed input signal and controlling a the first transistor, a third transistor connected in parallel to the second transistor, a fourth transistor coupled a gate of the third transistor for receiving the input signal and a charge circuit coupled between the delay circuit and the first node for supplying an electric charge to the first node. The charge circuit is activated in response to the potential level appeared on the first node and the delayed input signal.

Description

BACKGROUND OF THE INVENTION

This invention relates to a semiconductor integrated circuit such as a semiconductor memory or the like, and particularly to an output buffer circuit having a bootstrap circuit.

An output buffer circuit may have a bootstrap circuit. The bootstrap circuit is provided to output data at high speed and enhance driving capability. The output buffer circuit having the bootstrap circuit has been disclosed in Japanese Patent Application Laid-Open Publication No. 161921/84.

The disclosed output buffer circuit is provided with a bootstrap capacitor. When the bootstrap capacitor is discharged, a potential applied to the gate of an output transistor is raised. A power source potential supplied to the drain of the output transistor is supplied to other circuit through the source of the output transistor without a reduction in the power source potential with an increase in the potential applied to the gate of the output transistor.

There has recently been a demand for the appearance of an output buffer circuit which is simple in circuit configuration and capable of outputting data at high speed.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an output buffer circuit which is simple in circuit configuration and capable of outputting data at high speed.

The output buffer circuit according to the present invention comprises an input terminal for receiving an input signal, an output circuit coupled to a first node for outputting an output signal in response to a potential level appeared on the first node and a bootstrap circuit coupled between the first node and the input terminal.

The bootstrap circuit comprises a delay circuit, a first transistor. a second transistor, a third transistor, a fourth transistor and a charge circuit. The delay circuit couples to the input terminal for delaying the input signal to provide a delayed input signal. The first transistor has a drain electrode coupled to the first node, a source electrode coupled for receiving a signal inverted from the input signal and a gate electrode. The second transistor has a source electrode couples for receiveing the delayed input signal, a gate electrode coupled for receiving a first potential level and a drain electrode coupled to the gate electrode of the first transistor. The third transistor has a source electrode connected in parallel to the second transistor. The fourth transistor has a source electrode coupled for receiving the input signal, a drain electrode coupled to the gate electrode of the third transistor and a gate electrode coupled for receiving the first potential level. The charge circuit couples between the delay circuit and the first node for supplying an electric charge to the first node. The charge circuit is activated in response to the potential level appearing on the first node and the delayed input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an output buffer circuit according to the present invention; and

FIG. 2 is a timing chart for describing the operation of the output buffer circuit shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The configuration of an output buffer circuit according to the present invention will hereinafter be described with reference to FIG. 1.

The output buffer circuit 100 shown in FIG. 1 is used in a semiconductor memory such as a dynamic random access memory (DRAM) or the like. The output buffer circuit 100 comprises a bootstrap circuit 110, an inverter 120, an output buffer 130 and an output terminal 140. The bootstrap circuit 110 is supplied with an input signal DOH.sub.N and outputs a signal indicative of a boosted voltage therefrom. The inverter 120 receives an input signal DOL.sub.N therein and outputs a signal obtained by inverting the level of the input signal DOL.sub.N. The output buffer 130 is supplied with the boosted-voltage signal and the inverted signal and outputs a signal corresponding to the levels of the boosted-voltage signal and the inverted signal to an output terminal 140.

Circuit configurations of respective components employed in the output buffer circuit will now be described in detail.

The bootstrap circuit 110 comprises an inverter 11, three n-channel MOS transistors (hereinafter called "nMOSs") 12 through 14 which serve as delay means and a p-channel MOS transistor (hereinafter called a "pMOS") 15, an nMOS 16, two nMOSs 17 and 18 each of which serves as an output means, two nMOSs 19 and 20 which serve as charging and discharging means respectively, a boost capacitor 21, and two nMOSs 22 and 23.

The inverter 11 has an input electrically connected to a node N1 for receiving the input signal DOH.sub.N and an output electrically connected to a node N2. The inverter 11 supplies the reverse of the input signal DOH.sub.N to the node N2.

The gate and source of the nMOS 12 are electrically connected to the node N2 and a node N3 respectively. The drain of the nMOS 12 is supplied with a power source potential V.sub.CC. The gate and drain of the nMOS 13 are electrically connected to the nodes N1 and N3 respectively. The source of the nMOS 13 is supplied with a ground potential V.sub.SS. The gate and drain of the nMOS 14 are electrically connected to the node N3 and a node N4 respectively. The source of the nMOS 14 is supplied with the ground potential V.sub.SS. The gate and drain of the pMOS 15 are electrically connected to the nodes N2 and N4 respectively. The source of the nMOS 15 is supplied with the power source potential V.sub.CC. When a signal having a high potential such as the power source potential V.sub.CC (hereinafter called a "V.sub.CC level"), which is sufficient to activate the nMOS 13, is supplied to the node N1 as the input signal DOH.sub.N, the nMOS 13 is brought into an activated state. With the activation of the nMOS 13, the reverse of the input signal DOH.sub.N supplied to the node N2, for example, a signal having the ground potential V.sub.SS (hereinafter called a "V.sub.SS level") is supplied to the node N2. When the potential at the node N2 is brought to the V.sub.SS level, the nMOS 13 is inactivated. Thus, the pMOS 15 is brought into the activated state. When the pMOS 15 is activated, the ground potential V.sub.SS is supplied to the node N3 through the nMOS 13. When the potential at the node N3 is brought to the V.sub.SS level, the nMOS 14 is made inactive. The power source potential V.sub.CC is supplied to the node N4 through the pMOS 15 according to the change of states of the nMOSs 14 and 15. In other words, a potential having the V.sub.CC level identical to that of the input signal DOH.sub.N is supplied to the node N4 with a time delay. When, on the other hand, a signal having a potential of the V.sub.SS level is supplied to the node N1 as the input signal DOH.sub.N, the nMOSs 12 through 14 and the pMOS 15 are reversely activated. The potential of the V.sub.SS level identical to that of the input signal DOH.sub.N is supplied to the node N4 with a time delay according to the states of the nMOSs 12 through 14 and the pMOS 15.

The source of the nMOS 16 is electrically connected to the node N4, whereas the drain thereof is electrically connected to the gate of the nMOS 17. The gate of the nMOS 16 is supplied with the power source potential V.sub.CC. When the potential supplied to the node N4 is of the V.sub.CC level, the nMOS 16 supplies a potential V.sub.CC -V.sub.T16 (where V.sub.T16 represents the threshold value of the nMOS 16) to the gate of the nMOS 17.

The drain of the nMOS 17 is electrically connected to the node N2, whereas the source thereof is electrically connected to a node N5. The gate and drain of the nMOS 18 are electrically connected to the nodes N1 and N5 respectively. The source of the nMOS 18 is supplied with the ground potential V.sub.SS. When the signal having the potential of the V.sub.CC level is supplied to the node N1 as the input signal DOH.sub.N, the nMOS 18 is activated. As described above, the nMOS 17 is also activated when the potential at the node N4 is brought to the V.sub.CC level. Further, when the signal having the potential of the V.sub.SS level is supplied to the node N1 as the input signal DOH.sub.N, the nMOS 18 is brought into an inactivated state. As mentioned above, the nMOS 17 is also inactivated when the potential at the node N4 is brought to the V.sub.SS level.

The gate of the nMOS 19 is electrically connected to the node N4, whereas the drain thereof is electrically connected to a node N6. The source of the nMOS 19 is supplied with the ground potential V.sub.SS. The gate and source of the nMOS 20 are electrically connected to the nodes N5 and N6 respectively. The drain of the nMOS 20 is supplied with the power source V.sub.CC. The boost capacitor 21 has two electrodes one of which is electrically connected to the node N5 and the other of which is electrically connected to the node N6. When the potential of the input signal DOH.sub.N is of the V.sub.CC level, the one electrode of the boost capacitor 21 is supplied with the ground potential V.sub.SS under the activation of the nMOS 18. The potential at the node N2, which has been time-delayed by the inverter 11, becomes the V.sub.SS level. After the potential at the node N2 has been brought to the V.sub.SS level, the potential at the node N4 is brought to the V.sub.CC level by the delay means (nMOSs 12 through 14 and pMOS 15). Each of the nMOSs 17 and 19 is activated depending on the potential at the node N4. When the nMOS 19 is made active, the potential at the node N6 becomes the V.sub.SS level. In other words, the ground potential V.sub.SS is supplied to the other electrode of the boost capacitor 21. Since the ground potential V.sub.SS is supplied to both electrodes of the boost capacitor 21, the boost capacitor 21 is not charged. When the potential of the input signal DOH.sub.N is then brought to the V.sub.SS level, the nMOS 18 is inactivated. When the nMOS 18 is brought into the inactivated state, the potential at the node N2 still remains at the V.sub.SS level and the potential at the node N4 still remains at the V.sub.CC level. Since the potentials at the nodes N2 and N4 remain unchanged, the nMOSs 17 and 19 remain activated. According to the states of the nMOSs 17 and 19, the node N5 remains supplied with the potential at the node N2 through the nMOS 17, whereas the node N6 remains supplied with the ground potential V.sub.SS. The potential at the node N2, which has been delayed in time, is brought to the V.sub.CC level. When the potential at the node N2 reaches the V.sub.CC level, the potential at the node N4 still remains at the V.sub.CC level. Since the potential at the node N4 remains unchanged, each of the nMOSs 17 and 19 is maintained at the activated state. According to the states of the nMOSs 17 and 19, the node N5 remains supplied via the nMOS 17 with the potential at the node N2, which has been brought to the V.sub.CC level, whereas the node N6 remains supplied with the ground potential V.sub.SS. Since the ground potential V.sub.SS is supplied to the one electrode of the boost capacitor 21 and the potential at the node N2, which has been brought to the V.sub. SS level, is supplied to the other electrode of the boost capacitor 21 through the nMOS 17, the boost capacitor 21 is charged. After the potential at the node N2 has been brought to the V.sub.CC level, the potential at the node N4 is also brought to the V.sub.SS level by the delay means (nMOSs 12 through 14 and pMOS 15). Each of the nMOSs 17 and 19 is also brought into the inactivated state depending on the potential at the node N4. The node N5 is maintained at the potential at the node N2, which is supplied thereto through the nMOS 17, under the inactivation of the nMOSs 17 and 19. Further, the nMOS 20 is activated. When the nMOS 20 is activated, the node N6 is supplied with a potential V.sub.CC -V.sub.T20 (where V.sub.T20 represents the threshold value of the nMOS 20) through the nMOS 20. Since the potential V.sub.CC -V.sub.T20 is supplied to the one electrode of the boost capacitor 21 and the potential at the node N2, which has been brought to the V.sub.CC level by the nMOS 17, is supplied to the other electrode of the boost capacitor 21, the boost capacitor 21 is discharged, so that the potential at the node N5 is boosted. The signal having the potential at the node N5 is output as the boosting signal.

The drain of the nMOS 22 is electrically connected to the gate of the nMOS 23, whereas the source thereof is electrically connected to the node N1. The gate of the nMOS 22 is supplied with the power source V.sub.CC. The source of the nMOS 23 is electrically connected to the node N4, whereas the drain thereof is electrically connected to the gate of the nMOS 17. When the potential of the input signal DOH.sub.N is of the V.sub.CC level, a potential V.sub.CC -V.sub.T22 (where V.sub.T22 represents the threshold value of the nMOS 22) is supplied to the gate of the nMOS 23 through the nMOS 22. Thus, the nMOS 23 is activated in response to the potential V.sub.CC -V.sub.T22. When the potential of the input signal DOH.sub.N is brought to the V.sub.SS level, the nMOS 23 is inactivated.

The output buffer 130 comprises two nMOSs 31 and 32. The gate of the nMOS 31 is electrically connected to the node N5 of the bootstrap circuit 110, whereas the source thereof is electrically connected to the output terminal 140. The drain of the nMOS 31 is supplied with the power source potential V.sub.CC. The gate of the nMOS 32 is electrically connected to the output of the inverter 120, whereas the drain thereof is electrically connected to the output terminal 140. The source of the nMOS 32 is supplied with the ground potential V.sub.SS. Thus, each of the nMOSs 31 and 32 is activated or inactivated based on the boosting signal and the inverted signal. The output buffer 130 supplies either the power source potential V.sub.CC or the ground potential V.sub.SS to the output terminal 140 according to the states of the nMOSs 31 and 32.

The operation of the output buffer circuit 100 according to the present invention will now be described in detail with reference to FIG. 2. FIG. 2 is a timing chart for describing the operation of the output buffer circuit 100 according to the present invention. A waveform at the node N7, which shows the potential applied to the gate of the nMOS 17, and a waveform at the node N8, which shows the potential applied to the gate of the nMOS 23, are illustrated in FIG. 2 to easily understand the operation of the output buffer circuit 100.

The input signals DOH.sub.N and DOL.sub.N are out of phase with each other. The two signals DOH.sub.N and DOL.sub.N are respectively maintained at the V.sub.CC level during a non-operating period T.sub.0. Since the gate of the nMOS 32 is supplied with the ground potential V.sub.SS, the nMOS 32 is brought into the inactivated state. Further, since the potential at the node N1 is of the V.sub.CC level, the nMOSs 13 and 18 are brought into the activated state. The potentials at the nodes N3 and N5 reach the V.sub.SS level according to the states of the nMOSs 13 and 18. Since the gate of the nMOS 31 is also supplied with the ground potential V.sub.SS, the nMOS 31 is inactivated. Thus, the output terminal 140 is brought into a floating state (i.e., a predetermined potential V.sub.R (where V.sub.SS <V.sub.R <V.sub.CC)) depending on the states of the nMOSs 31 and 32. The potential at a node N8 is of V.sub.CC -V.sub.T22. Since the potential at the node N2 becomes V.sub.SS, the pMOS 15 is inactivated. The potential at the node N4 is brought to the V.sub.CC level according to the state of the pMOS 15. The gate of the nMOS 23 is supplied with the potential V.sub.CC -V.sub.T22 before the potential at the node N4 reaches the V.sub.CC level. The potential supplied to the source of the nMOS 23 is raised from V.sub.SS to V.sub.CC depending on the potential at the node N4. Thus, the potential at the node N8 is raised from V.sub.CC -V.sub.T22 to V.sub.CC -V.sub.T22 +V.sub.G23 (where V.sub.G23 represents a potential boosted based on the gate capacitance provided between the gate and source of the nMOS 23 and is equal to or greater than V.sub.T22 (i.e., V.sub.G23 .gtoreq.V.sub.T22)) based on the gate capacitance created therebetween in response to an increase in potential supplied to the source of the nMOS 23. The potential at the node N7 is brought to the potential (V.sub.CC) at the node N4 in response to the increase in the potential at the node N8. Further, the potential at the node N6 is brought to the V.sub.SS level according to the potential at the node N4.

When the potential of the input signal DOH.sub.N then reaches the V.sub.SS level during an operating period T.sub.1, the potential at the node N1 is changed to the V.sub.SS level. The potential at the node N8 is brought to the V.sub.SS level depending upon the potential at the node N8. The nMOS 23 is deactivated and the nMOSs 13 and 18 are inactivated in response to the potential at the node N1. After the input signal has been time-delayed by the inverter 11, the potential at the node N2 is changed to the V.sub.CC level. With N2 at V.sub.CC the nMOS 12 is brought into the activated state according to the potential at the node N2. When the potential at the node N2 reaches the V.sub.CC level, the potential at the node N4 still remains at the V.sub.CC level. A potential V.sub.CC -V.sub.T17 (where V.sub.T17 represents the threshold potential of the nMOS 17) corresponding to the potential at the node N2 is supplied to the node N5 through the nMOS 17 activated according to the potentials at the nodes N2 and N4. Thus, the nMOS 20 and the nMOS 31 of the output buffer 130 are activated in response to the potential at the node N8. The potential at the output terminal 140 is raised according to the activated state of the nMOS 31. Simultaneously with an increase in the potential at the output terminal 140, the potential supplied to the source of the nMOS 17 is raised from the V.sub.SS level to the V.sub.CC -V.sub.T17 level in a state in which the gate of the nMOS 17 has been supplied with the potential V.sub.CC. Based on the gate capacitance created between the gate and source of the nMOS 17, the potential supplied to the gate of the nMOS 17 is raised from the V.sub.CC level to a V.sub.CC +V.sub.G17 (where V.sub.G17 represents a potential boosted based on the gate capacitance created between the gate and source of the nMOS 17 and is equal to or greater than V.sub.T17 (i.e., V.sub.G17 .gtoreq.V.sub.T17)) level. The potential at the node N5 is boosted to the potential (V.sub.CC level) at the node N2 according to the increase in the potential of the gate of the nMOS 17. The potential at the output terminal 140 is brought to V.sub.CC -V.sub.T31 (where V.sub.T31 represents the threshold potential of the nMOS 31) according to the increase in the potential at the node N8. The potential at the node N3 becomes V.sub.CC -V.sub.T12 (where V.sub.T12 represents the threshold potential of the nMOS 12) based on the potential at the node N2. The nMOS 14 is activated in response to the potential at the node N3 and the potentials at the nodes N4 and N7 are changed to the V.sub.SS level. Each of the nMOSs 17 and 19 is inactivated in response to the potential at the node N4. The potential at the node N5 is maintained at the V.sub.CC level according to the state of each of the nMOSs 17 and 19, whereas the potential at the node N6 is changed to the V.sub.CC -V.sub.T20 level. Thus, the boost capacitor 21 is discharged in response to an increase in the potential at the node N6. With the discharge of the boost capacitor 21, the potential at the node N5 is raised from the V.sub.CC level to a V.sub.CC +V.sub.G21 (where V.sub.G21 represents a potential boosted based on the capacitance of the boost capacitor 21 and is equal to or greater than V.sub.T31 (i.e., V.sub.G21 .gtoreq.V.sub.T31)) level. Thus, the potential supplied to the gate of the nMOS 31 of the output buffer 130 is raised with the increase in the potential at the node N5. Further, the potential at the output terminal 140 is changed from the V.sub.CC -V.sub.T31 level to the V.sub.CC level in response to the increase in the potential applied to the gate of the nMOS 31. In other words, the output buffer circuit 100 can produce a signal having a sufficient potential.

When the input signal DOH.sub.N is brought to the V.sub.CC level during a reset period T2, the potential at the node N1 reaches the V.sub.CC level. Thus, each of the nMOSs 13 and 18 is activated in response to the potential at the node N1. Further, the potential at each of the nodes N3 and N5 is brought to the V.sub.SS level depending on the state of each of the nMOSs 13 and 18. The gate of the nMOS 31 is also supplied with the ground potential V.sub.SS depending on the potential at the node N5. Thus, since the nMOS 31 is brought into the inactivated state, the output terminal 140 is brought into the floating state (i.e., the predetermined potential V.sub.R (where V.sub.SS <V.sub.R <V.sub.CC)). Further, the potential at the node N8 is brought to the V.sub.CC -V.sub.T22. Since the potential at the node N2 reaches the V.sub.SS level, the pMOS 15 is brought into the inactivated state. The potential at the node N4 is brought to the V.sub.CC level depending on the state of the pMOS 15. The gate of the nMOS 23 is supplied with the potential V.sub.CC -V.sub.T22 before the potential at the node N4 reaches the V.sub.CC level. The potential supplied to the source of the nMOS 23 is raised from the V.sub.SS level to the V.sub.CC level in response to the potential at the node N4. The potential at the node N8 is raised from the V.sub.CC -V.sub.T22 to the V.sub.CC -V.sub.T22 +V.sub.G23 based on the gate capacitance created between the gate and source of the nMOS 23 in response to the increase in the potential supplied to the source of the nMOS 23. Since the nMOS 23 has the mutual conductance gm larger than that of the nMOS 16, the node N7 is brought to the potential (V.sub.CC) at the node N4 while following the potential level of the node N4. In other words, the potential at the node N7 becomes the V.sub.CC level even during a short reset period. During the operating period, the bootstrap circuit 110 makes it possible to stably set the node N5 to a predetermined potential. The potential at the node N6 is brought to the V.sub.SS level in response to the potential at the node N4.

The present invention is not necessarily limited to the above-described embodiment. For example, the polarity of the power source employed in the bootstrap circuit 110 may be changed so that each nMOS be replaced by each pMOS. The elements of structure employed in the output buffer 130 may be replaced with other transistors. Further, other elements may be additionally provided to make the charging or discharging rate of the bootstrap capacitor 21 faster.

Claims

1. An output buffer circuit comprising:

an input terminal for receiving an input signal;

an output circuit coupled to a first node for outputting an output signal in response to a potential level appearing on the first node; and

a bootstrap circuit coupled between the first node and the input terminal, comprising:

a delay circuit coupled to the input terminal for delaying the input signal to provide a delayed input signal:

a first transistor having a drain electrode coupled to the first node, a source electrode coupled for receiving a signal inverted from the input signal, and a gate electrode,

a second transistor having a source electrode coupled for receiving the delayed input signal, a gate electrode coupled for receiving a first potential level and a drain electrode coupled to the gate electrode of the first transistor;

a third transistor connected in parallel to the second transistor, the third transistor having a gate electrode;

a fourth transistor having a source electrode coupled for receiving the input signal, a drain electrode coupled to the gate electrode of the third transistor, and a gate electrode coupled for receiving the first potential level:

a charge circuit coupled between the delay circuit and the first node for boosting to the first node in response to the potential level appearing on the first node and the delayed input signal.

2. An output buffer circuit according to claim 1, wherein the output circuit includes a MOS transistor having a gate electrode coupled to the first node, a source electrode for outputting the output signal and a drain electrode supplied a power source potential.

3. An output buffer circuit according to claim 1, wherein the third transistor boosts the potential level appearing on the gate electrode thereof when the delayed input signal changes from a low level to a high level.

4. An output buffer circuit according to claim 1, wherein the first transistor boosts the potential level appeared on the gate electrode thereof when the inverted input signal changes from a low level to a high level.

5. An output buffer circuit according to claim I, wherein the charge circuit has a capacitor having a first electrode and a second electrode coupled to the first node, a fifth transistor having a gate electrode coupled for receiving the delayed input signal and a drain electrode coupled to the first electrode of the capacitor, and a sixth transistor having a gate electrode coupled to the first node and a source electrode coupled to the first electrode of the capacitor.

6. An output buffer circuit according to claim 1, wherein the first potential level is power source potential level.

7. An output buffer circuit comprising:

an input terminal for receiving an input signal;

an output circuit coupled to a first node for outputting an output signal in response to a potential level appearing on the first node: and

a bootstrap circuit coupled between the first node and the input terminal, comprising:

a delay circuit coupled to the input terminal for delaying the input signal to provide a delayed input signal:

a first transistor having a drain electrode coupled to the first node, a source electrode coupled for receiving a signal inverted from the input signal, and a gate electrode,

a transfer circuit coupled between the delay circuit and the gate electrode of the first transistor for supplying the delayed input signal to the gate of the first transistor when the delayed input signal changes from a low level to a high level, the transfer circuit being activated in response of the input signal:

a second transistor having a source electrode coupled for receiving the input signal, a drain electrode coupled to the transfer circuit, and a gate electrode coupled for receiving the first potential level;

a charge circuit coupled between the delay circuit and the first node for boosting the first node in response to the potential level appearing on the first node and the delayed input signal.

8. An output buffer circuit according to claim 7, wherein the transfer circuit includes a third transistor having a source electrode coupled for receiving the delayed input signal, a gate electrode coupled for receiving the potential level and a drain electrode coupled to the gate electrode of the first transistor, and a fourth transistor connected in parallel to the third transistor, the fourth transistor having a gate electrode.

9. An output buffer circuit according to claim 8, wherein the fourth transistor boosts the potential level appearing on the gate electrode thereof when the delayed input signal changes from a low level to a high level.

10. An output buffer circuit according to claim 8, wherein the first potential level is power source potential level.

11. An output buffer circuit according to claim 7, wherein the output circuit includes a MOS transistor having a gate electrode coupled to the first node, a source electrode for outputting the output signal and a drain electrode supplied a power source potential.

12. An output buffer circuit according to claim 7, wherein the first transistor boosts the potential level appearing on the gate electrode thereof when the inverted input signal changes from a low level to a high level.

13. An output buffer circuit according to claim 7, wherein the charge circuit has a capacitor having a first electrode and a second electrode coupled to the first node, a fifth transistor having a gate electrode coupled for receiving the delayed input signal and a drain electrode coupled to the first electrode of the capacitor, and a sixth transistor having a gate electrode coupled to the first node and a source electrode coupled to the first electrode of the capacitor.