An Integrated Circuit (IC) is typically made up of individual electrical elements and typically includes active elements such as one or more transistor devices. Typical operation of a transistor requires connection of the transistors either directly or through other electrical devices to a high and a low output of a voltage supply. Typically, the high output of the voltage supply is identified as the high voltage supply and the low output of the voltage supply is identified as the low voltage supply. For an IC based on Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), it is common to refer to the high supply voltage as VDD (or VDDIO as used within this document) and to refer to the low supply voltage as VSS. Many if not most, times VSS is also referred to and defined as the electrical ground for a circuit. Typical operation of a MOSFET device involves the application of high (VDD) and or low (VSS) supply voltages to the gate, source, and/or drain either directly or through other electrical circuit devices. MOSFET devices are typically divided into two major subdivisions, PMOS devices and NMOS devices which have related, but different operation characteristics. While initially tied to MOSFET based circuits, the use of VDD and VSS to represent the high and low voltage outputs, respectively, has become common usage even for non-MOSFET based circuits.
An embodiment of the present invention may comprise a method to provide a bounded bias voltage with improved Process-Voltage-Temperature (PVT) adjustment comprising: generating a PVT adjusted bias_n voltage at a bias_n output of a bias_n voltage generation circuit that adjusts for Process-Voltage-Temperature (PVT) as a function of temperature affected voltages of a first bias_n NMOS diode (MNBN1) and a second bias_n NMOS diode (MNBN2), the generation of the bias_n voltage further comprising: connecting in series between a high voltage supply (VDDIO) and a low voltage supply (VSS) the following electrical components in the following order: a first bias_n resistor (RN1), a first bias_n NMOS diode (MNBN1), a second bias_n NMOS diode (MNBN2), and a second bias_n resistor (RN2), connected such that the first bias_n NMOS diode (MNBN1) and the second bias_n NMOS diode (MNBN2) are placed to permit current to flow from the high voltage supply (VDDIO) to the low voltage supply (VSS) and a resistance of the first bias_n resistor (RN1) is substantially equal to a resistance of the second bias_n resistor (RN2); connecting the bias_n voltage output substantially electrically at the junction/connection between the first bias resistor (RN 1) and the first bias_n NMOS diode (MNBN1) in order to permit Process-Voltage-Temperature (PVT) variations of threshold voltages that vary with temperatures of the first (MNBN1) and the second (MNBN2) bias_n NMOS diodes to vary the PVT adjusted bias_n voltage at the bias_n voltage output; and operating the high voltage supply (VDDIO) and the low voltage supply (VSS) such that the PVT adjusted bias_n voltage is generated at the bias_n output of the bias_n voltage generation circuit; generating a PVT adjusted bias_p voltage at a bias_p output of a bias_p voltage generation circuit as a function of temperature affected voltages of a first bias_p PMOS transistor (MPBP1) and a second bias_p PMOS transistor (MPBP2), the generation of the bias_p voltage further comprising: connecting in series between the high voltage supply (VDDIO) and the low voltage supply (VSS) the following electrical components in the following order: a first bias_p resistor (RP1), a first bias_p PMOS diode (MPBP1), a second bias_p PMOS diode (MPBP2), and a second bias_p resistor (RP2), connected such that the first bias_p PMOS diode (MPBP1) and the second bias_p PMOS diode (MPBP2) are placed to permit current to flow from the high voltage supply (VDDIO) to the low voltage supply (VSS) and a resistance of the first bias_p resistor (RP1) is substantially equal to a resistance of the second bias_p resistor (RP2); connecting the bias_p voltage output substantially electrically at the junction/connection between the second bias_p PMOS diode (MPBP2) and the second bias_p transistor (RP2) in order to permit Process-Voltage-Temperature (PVT) variations of threshold voltages that vary with temperatures of the first (MPBP1) and the second (MPBP2) bias_p PMOS diodes to vary the PVT adjusted bias_p voltage at the bias_p voltage output; and operating the high voltage supply (VDDIO) and the low voltage supply (VSS) such that the PVT adjusted bias_p voltage is generated at the bias_p output of the bias_p generation voltage generation circuit; generating a PVT adjusted bounded bias voltage at a bounded bias voltage output of a bounded bias voltage generation circuit, the generation of the bounded bias voltage further comprising: connecting a drain of a first bounded bias NMOS transistor (MN1) to the high voltage supply (VDDIO); connecting a gate of the first bounded bias NMOS transistor (MN1) to the bias_n voltage output of the bias_n voltage generation circuit such that the PVT adjusted bias_n voltage is applied to the gate of the first bounded bias NMOS transistor (MN1); connecting a source of the first bounded bias NMOS transistor (MNBB 1) to a source of a first bounded bias PMOS transistor (MPBB 1) such that the common connection of the source of the first bounded bias NMOS transistor (MNBB1) and the source of the first bounded bias PMOS transistor (MPBB1) substantially electrically comprise the bounded bias voltage output of the bounded bias voltage generation circuit; connecting a gate of the first bounded bias PMOS transistor (MPBB1) to the bias_p voltage output of the bias_p voltage generation circuit such that the PVT adjusted bias_p voltage is applied to the gate of the first bounded bias PMOS transistor (MPBB 1); connecting a drain of the first bounded bias PMOS transistor (MPBB1) to the low voltage supply (VSS); and operating the high voltage supply (VDDIO), the low voltage supply (VSS), the bias_n voltage generation circuit, and the bias_p voltage generation circuit such that the PVT adjusted bounded bias voltage is generated at the bounded bias voltage output of the bounded bias voltage generation circuit.
An embodiment of the present invention may further comprise a bounded bias voltage apparatus that provides a bounded bias voltage with improved Process-Voltage-Temperature (PVT) adjustment comprising: a bias_n voltage generation circuit that generates a PVT adjusted bias_n voltage at a bias_n output of the bias_n voltage generation circuit that adjusts for Process-Voltage-Temperature (PVT) as a function of temperature affected voltages of a first bias_n NMOS diode (MNBN1) and a second bias_n NMOS diode (MNBN2), the bias_n voltage generation circuit further comprising: a first bias_n resistor (RN1), a first bias_n NMOS diode (MNBN1), a second bias_n NMOS diode (MNBN2), and a second bias_n resistor (RN2) connected in order in series between a high voltage supply (VDDIO) and a low voltage supply (VSS), further connected such that the first bias_n NMOS diode (MNBN1) and the second bias_n NMOS diode (MNBN2) are placed to permit current to flow from the high voltage supply (VDDIO) to the low voltage supply (VSS) and a resistance of the first bias_n resistor (RN1) is substantially equal to a resistance of the second bias_n resistor (RN2), the bias_n voltage output connected substantially electrically at the junction/connection between the first bias resistor (RN1) and the first bias_n NMOS diode (MNBN1) in order to permit Process-Voltage-Temperature (PVT) variations of threshold voltages that vary with temperatures of the first (MNBN1) and the second (MNBN2) bias_n NMOS diodes to vary the PVT adjusted bias_n voltage at the bias_n voltage output, and such that operation of the high voltage supply (VDDIO) and the low voltage supply (VSS) generates the PVT adjusted bias_n voltage at the bias_n output of the bias_n voltage generation circuit; a bias_p voltage generation circuit that generates a PVT adjusted bias_p voltage at a bias_p output of the bias_p voltage generation circuit as a function of temperature affected voltages of a first bias_p PMOS transistor (MPBP1) and a second bias_p PMOS transistor (MPBP2), the bias_p voltage generation circuit further comprising: a first bias_p resistor (RP1), a first bias_p PMOS diode (MPBP1), a second bias_p PMOS diode (MPBP2), and a second bias_p resistor (RP2) connected in order in series between the high voltage supply (VDDIO) and the low voltage supply (VSS), further connected such that the first bias_p PMOS diode (MPBP1) and the second bias_p PMOS diode (MPBP2) are placed to permit current to flow from the high voltage supply (VDDIO) to the low voltage supply (VSS) and a resistance of the first bias_p resistor (RP1) is substantially equal to a resistance of the second bias_p resistor (RP2), the bias_p voltage output connected substantially electrically at the junction/connection between the second bias_p PMOS diode (MPBP2) and the second bias_p transistor (RP2) in order to permit Process-Voltage-Temperature (PVT) variations of threshold voltages that vary with temperatures of the first (MPBP1) and the second (MPBP2) bias_p PMOS diodes to vary the PVT adjusted bias_p voltage at the bias_p voltage output, and such that operation of the high voltage supply (VDDIO) and the low voltage supply (VSS) generates the PVT adjusted bias_p voltage at the bias_p output of the bias_p generation voltage generation circuit; a bounded bias voltage generation circuit that generates a PVT adjusted bounded bias voltage at a bounded bias voltage output of the bounded bias voltage generation circuit, the bounded bias voltage generation circuit further comprising: a first bounded bias NMOS transistor (MNBB1) having a drain connected to the high voltage supply (VDDIO), having a gate connected to the bias_n voltage output of the bias_n voltage generation circuit such that the PVT adjusted bias_n voltage is applied to the gate of the first bounded bias NMOS transistor (MNBB1); a first bounded bias PMOS transistor (MPBB1) having a source connected to a source of the first bounded bias NMOS transistor (MNBB1) such that the common connection of the source of the first bounded bias NMOS transistor (MNBB1) and the source of the first bounded bias PMOS transistor (MPBB 1) substantially electrically comprise the bounded bias voltage output of the bounded bias voltage generation circuit, the first bounded bias PMOS transistor (MPBB 1) further having a gate connected to the bias_p voltage output of the bias_p voltage generation circuit such that the PVT adjusted bias_p voltage is applied to the gate of the first bounded bias PMOS transistor (MPBB1), the first bounded bias PMOS transistor (MPBB1) further having a drain connected to the low voltage supply (VSS), and such that operation of the high voltage supply (VDDIO), the low voltage supply (VSS), the bias_n voltage generation circuit, and the bias_p voltage generation circuit generates the PVT adjusted bounded bias voltage at the bounded bias voltage output of the bounded bias voltage generation circuit.
In the drawings,
When electronic devices first began to use Integrated Circuits (ICs) to provide the functionality for the end electronic device (i.e., the end device), a typical application obtained power from a wall plug, which essentially amounted to an unlimited power source for the end device. Relatively quickly, consumer demand for portable devices not dependent on a wall plug resulted in end devices being powered by various battery systems that represented finite power sources relative to the end device. Thus, there came a drive to make the ICs as energy efficient as possible so as to extend the life of the end device by using less battery power. One way IC manufacturers reduced power consumption on the ICs was to reduce the voltage requirements for the IC logic and power supplies. For instance, 5 volt logic/supplies may have migrated to 3.3 volt logic/supplies, and then migrated further to 1.7 volt logic/supplies.
While some IC chips may operate at lower voltages, it is not uncommon for one or more other IC chips necessary to provide the overall desired functionality of an end device to operate at one of the older/higher voltages. Further, as standards are slower to change than individual pieces of technology (e.g., particular IC chips), some Input/Output (JO) communication standards often require higher voltages than many of the IC chips that drive the logic/end device implementing the communication standard, Thus, for many systems, it may be beneficial to have two, or more, voltage supplies to operate the various components and sub-components of the system. However, it is often undesirable to have to implement two or more voltage supplies and the required traces/wiring necessary to supply the multiple voltage supplies on a system. Therefore, it may be desirable for a system to implement a voltage conditioning system that converts a high voltage supply to a lower voltage to power an individual device. The voltage conditioning circuitry may be implemented either outside the lower voltage IC-component-device, or, preferably to the end user, the voltage conditioning circuitry may be included at the voltage supply input for the lower voltage IC-component-device. Further, it may also be desirable to have both high voltage and low voltage circuitry in an individual IC, so an IC may implement the lower voltage conditioning circuitry for a portion/sub-system of the IC while still permitting other circuitry to use the higher voltage supply.
While the resistor divider circuit 100 shown in
While a system such as the circuit 200 shown in
Resistors RN1 (312) and RN2 (320) should have substantially equal resistance values for the various embodiments. Thus, for an overall resistance of RN, RN1 (312) substantially equals one half of RN, and RN2 (320) also substantially equals one half of RN. The NMOS bias_n transistors MNBN1 (314) and MNBN2 (316) are connected as NMOS diodes 314, 316 in series between the high voltage supply VDDIO 302 and the low voltage supply VSS 304 such that the NMOS diodes 314, 316 are placed such that current (i.e., the variable “I” in mathematical representations of the circuit) is permitted to flow from the high voltage supply VDDIO 302 to the low voltage supply VSS 304. The resistors RN1 (312) and RN2 (320) are also connected in series with the NMOS diodes 314, 316 such that RN1 (312) is placed between the transistor/diode MNBN1 (314) and VDDIO 302 and RN2 (320) is placed between the transistor/diode MNBN2 (320) and VSS 304. Thus, with the resistance RN split substantially in half between the NMOS bias_n transistors/diodes MNBN1 (314) and MNBN2 (316) and the high voltage supply VDDIO 302 as resistor RN1 (312), and half between the NMOS bias_n transistors/diodes MNBN1 (314) and MNBN2 (316) and the low voltage supply VSS 304 as RN2 (320), the two NMOS bias_n transistors/NMOS diodes are effectively body-biased. The bias_n voltage output (308) may be placed at the junction/connection between the first bias_n resistor RN1 (312) and the first NMOS bias_n transistor/NMOS diode MNBN1 (314). Further, the NMOS transistors/diodes MNBN1 (314) and MNBN2 (316) may be implemented using enhancement mode NMOS transistors. Thus, the PVT adjusted bias_n voltage generation circuit 300 shown in
Using Kirchhoff's laws, the bias_n voltage 308 generated by the PVT adjusted bias_n voltage generation circuit 300 may derived as follows in Eqs. 3-6 below, where “I” represents current flow through the bias_n generation circuit 300 and “Vt” represents the threshold voltage of the indicated NMOS transistor/diode device:
VDDIO=I×RN1+I×RN2+VtMNBN1+VtMNBN2 Eq. 3
And since RN1=RN2=RN/2:
As effectively body-biased devices, the threshold voltage (Vt) of the active component NMOS transistors/diodes MNBN1 (314) and MNBN2 (316) vary with the PVT variations. Further, assuming the threshold voltages of the two NMOS transistors/diodes 314, 316 are substantially equal, makes Eq. 6 the same as Eq. 2. Thus, the bias_n equation (Eq. 2 and/or Eq. 6) is effectively the average of two body-biased devices 314, 316, which provides enhanced operation (see, for example, the description with respect to
Resistors RP1 (334) and RP2 (340) should have substantially equal resistance values for the various embodiments. Thus, for an overall resistance of RP, RP1 (334) substantially equals one half of RP, and RP2 (340) also substantially equals one half of RP. It should be noted that it is not necessary for the overall resistance RP of the bias_p voltage generation circuit 380 shown in
Using Kirchhoff's laws, the bias_p voltage 310 generated by the PVT adjusted bias_p voltage generation circuit 380 may derived as follows in Eqs. 8-11 below, where “I” represents current flow through the bias_p generation circuit 380 and “Vt” represents the threshold voltage of the indicated PMOS transistor/diode device:
VDDIO=I×RP1+I×RP2+VtMPBP1+VtMPBP2 Eq. 8
And since RP1=RP2=RP/2:
As effectively body-biased devices, the threshold voltage (Vt) of the active component PMOS transistors/diodes MPBP1 (336) and MPBP2 (338) vary with the PVT variations. Further, assuming the threshold voltages of the two PMOS transistors/diodes 336, 338 are substantially equal, makes Eq. 11 the same as Eq. 7. Thus, the bias_p equation (Eq. 7 and/or Eq. 11) is effectively the average of two body-biased devices, which provides enhanced operation (see, for example, the description with respect to
A typical use for a PVT bounded bias voltage 306 may be to provide a lower voltage power supply for low voltage circuitry/devices from a high/higher voltage power supply for a high voltage device. Since the bounded bias voltage 306 of an embodiment has improved tracking with PVT variations, the lower voltage circuit is better able to track for process corners (i.e., worst case electrical system scenarios). Without proper PVT tracking for the threshold voltages (Vt), there is a risk of electrical currents in a circuit/device dropping to an unacceptably low value in a weak process corner. Thus, the PVT adjusted bounded bias voltage 306, permits a system to better avoid unacceptably low currents for weak process corners of low voltage circuits/devices.
Various embodiments may be implemented using components that have substantially electrically similar characteristics. For instance, in place of one resistor, multiple resistors may be included that together have the same resistance characteristics as the resistors described herein.
The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.