Claims
- 1. In a pipelined processor having a arithmetic and logic unit (ALU) for execution of decoded instructions, an instruction address generator (14) and an instruction address register (IAR) for holding an address for a next memory location to be accessed, the improvements for providing "branch to" addresses to said IAR, comprising:
- an instruction store (20) for storing sequential instructions, and means for loading into said instruction store instructions for sequential decoding;
- means (19) connected to said instruction store (20) for holding and outputting instructions to be decoded;
- branch decision logic means and instruction decoding logic means (21) connected to said means for holding and outputting for controlling selection of a "branch to" address for loading into said IAR, said address being supplied either by said ALU or said instruction address generator (14) and selected and loaded into said IAR in accordance with a result of said branch decision logic means and instruction decoding logic means (21) operating on a branch instruction during the time while the sequential instruction which immediately precedes said branch instruction is executing in said ALU.
Parent Case Info
This application is a continuation of application Ser. No. 723,594, filed Apr. 15, 1985, now abandoned.
US Referenced Citations (8)
Foreign Referenced Citations (1)
Number |
Date |
Country |
1193738 |
Sep 1985 |
CAX |
Continuations (1)
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Number |
Date |
Country |
Parent |
723594 |
Apr 1985 |
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