Patent Application
20140143526
Embodiments relate generally to branch prediction in computer processors.
Conventionally, program code executed by a processor will include branches, meaning conditional instructions that may cause the flow of execution to branch in one of two possible directions (e.g., an IF instruction). These two possible directions may be the “not taken branch” (i.e., processing continues in the next sequential portion of the code) and the “taken branch” (i.e., processing jumps to a different, non-sequential portion of the code).
A branch predictor is a circuit that tries to predict which way a branch will go before the actual direction of the branch has been determined. The predicted branch direction may then be used to fetch a set of instructions so that they can be staged for execution and/or speculatively executed before the branch has actually been evaluated. In this manner, the branch predictor may enable the processor pipeline to operate efficiently.
In accordance with some embodiments, gating of a branch prediction unit may be provided. In some embodiments, a distance between a first branch and a second branch may be determined using a distance counter. The distance value may be stored in a first branch entry of a target array. Subsequently, in response to a prediction for the first branch, the branch prediction unit may be gated until reaching the expected location of the second branch. Such gating may reduce the electrical power consumed by the branch prediction unit.
Referring to
As shown, in one or more embodiments, the processor 110 may include prediction gating logic 120. In accordance with one or more embodiments, the prediction gating logic 120 may provide functionality to gate or control the use of branch predictions in the processor 110.
In one or more embodiments, the prediction gating logic 120 may operate in two phases, a training phase and a prediction phase. In the training phase, the prediction gating logic 120 may collect historical information about the distances (e.g., number of instruction blocks, number of instructions, etc.) between branches found in program code. Further, in the prediction phase, the prediction gating logic 120 may gate the branch prediction functionality of the processor 110 based on the historical branch information (gathered during the training phase).
As shown, in some embodiments, the prediction gating logic 120 may include a distance counter 122, a halt counter 124, and a target array 126. In some embodiments, the distance counter 122 may be used during the training phase to determine a distance between a first branch and a second branch. This distance is then stored in a first branch entry (i.e., an entry of the target array 126 corresponding to the first branch). During the prediction phase, the halt counter 124 may be set equal to the distance value when the first branch is predicted to be taken. Branch predictions may then be gated until the halt counter 124 reaches zero, indicating the expected location of the second branch. Thus, in some embodiments, the electrical power required for branch predictions may be reduced during the period in which a branch is not expected. In this manner, the power level of the battery 135 may be conserved.
The functionality of the prediction gating logic 120 is described in greater detail below with reference to
Referring now to
As shown, in some embodiments, the BPU 170 includes prediction components 172, the target array 126, and the halt counter 124. Further, in some embodiments, the decode unit 150 may include the distance counter 122 and the last branch register 152. In one or more embodiments, the BPU 170 may use the various prediction components 172 (e.g., bimodal predictors, global predictors, local predictors, etc.) to generate different branch predictions, and may then select one of these predictions as being the most accurate and/or appropriate for use with the current branch. The BPU 170 may then use the selected prediction to determine the order in which the fetch unit 140 retrieves the instructions. In some embodiments, the particular prediction component 172 that provides the selected prediction may be referred to as the “preferred component” for the current branch.
During the training phase, beginning when the BPU 170 predicts that a first branch is to be taken, the distance counter 122 may count up for each instruction block retrieved by the fetch unit 140. Further, in some embodiments, an identifier for the first branch may be stored in the last branch register 152. Subsequently, when the BPU 170 predicts that a second branch is to be taken, the value of the distance counter 122 may be used as the distance between the first branch and the second branch. In some embodiments, the target array 126 may be updated to include a first branch entry (i.e., an entry corresponding to the first branch). The first branch entry may include a distance portion to store the value of the distance counter 122. Further, the first branch entry may also include a tag portion to store the first branch identifier (e.g., obtained from the last branch register 152). Furthermore, the first branch entry may also include a preferred component portion to store an identifier for the prediction component 172 selected by the BPU 170 for the second branch prediction. An example embodiment of the target array 126 is described below with reference to
During the prediction phase, when the BPU 170 again predicts that the first branch is to be taken, the halt counter 122 may be set equal to the distance value stored in the first branch entry of the target array 126. The halt counter 122 may then count down for each instruction block retrieved by the fetch unit 140. In one or more embodiments, the BPU 170 may be gated while the value of the halt counter 122 is greater than zero. Stated differently, until reaching the location of the second branch (as indicated by the halt counter 122 reaching zero), each instruction block is decoded and executed without performing a branch prediction. Accordingly, the electrical power required by the BPU 170 may be reduced or eliminated for processing the instruction blocks between the first and second branches.
When the value of the halt counter 122 reaches zero, the BPU 170 is no longer gated, and thus the BPU 170 may predict the second branch. In some embodiments, the BPU 170 may use only the prediction component 172 specified in the preferred component portion of the first branch entry of the target array 126. In this manner, the BPU 170 may avoid using other prediction components 172 to generate alternative predictions, and then selecting one of the alternative predictions. Accordingly, the electrical energy that would otherwise be required for generating and selecting such alternative predictions may be reduced or eliminated.
In one or more embodiments, all branch predictions are performed by the BPU 170. Alternatively, in some embodiments, branch predictions are divided between the BPU 170 and the decode unit 150. Specifically, the BPU 170 may provide predictions for direct branches, while the decode unit 150 may provide predictions for indirect branches. In such embodiments using divided branch predictions, the prediction gating logic 120 may set the distance value to a large number (e.g., 9999, 999999, etc.) when a direct branch is followed by an indirect branch in the training mode. Further, in the prediction mode, the halt counter 122 may be reset when the decode unit 150 provides a prediction for the indirect branch. Thus, in such embodiments, the BPU 170 is gated until the indirect branch is predicted.
Referring now to
In one or more embodiments, the tag portion 210 may include a tag identifier and/or an address for the current branch (i.e., the branch corresponding to the entry 205). In some embodiments, the tag identifier may be obtained from the last branch register 152 at the creation of the entry 205.
In some embodiments, the taken portion 220 may be an indication of whether the current branch has been predicted as taken. For example, the taken portion 220 may be a binary bit, a “yes/no” field, etc. Further, in some embodiments, the target portion 230 may include an identifier and/or address (e.g., an index and an offset) for the predicted target of the current branch.
In one or more embodiments, the distance portion 240 may include a distance value (e.g., a number of instruction blocks) from the current branch to the next branch. In some embodiments, the distance value stored in the distance portion 240 may be determined by the distance counter 122 (shown in
In some embodiments, the distance portion 240 may be an encoded version of the distance to the next branch. For example, assume that the distance portion 240 is configured to store a binary value in which each unit represents a distance of two instruction blocks. Assume further that the distance portion 240 of a given entry stores the binary value “10” (i.e., the decimal value “2”). Thus, in this example, the distance to the next branch may be decoded to be four instruction blocks. Optionally, in some embodiments, the decoded value of the distance portion 240 may be rounded down by one to account for odd distance values. In some embodiments, the encoding of the distance portion 240 may involve trimming one or more bits from a bit value of the distance to the next branch. Thus, in such embodiments, the number of bits required for the distance portion 240 may be reduced.
In one or more embodiments, the preferred component portion 250 may include an identifier for a prediction component used to predict the next branch (i.e., the branch located at the distance indicated by the distance portion 240). For example, the preferred component portion 250 may identify the prediction component 172 of the BPU 170 (shown in
Referring now to
At step 312, a first branch is predicted taken. For example, referring to
At step 314, a distance counter is initialized. For example, referring to
At step 316, the target of the first branch may be stored. For example, referring to
At step 318, the distance counter may be incremented for each instruction block until a second branch is predicted taken. For example, referring to
At step 320, the value of the distance counter may be stored in a target array entry for the first branch. For example, referring to
At step 322, an identifier for the preferred component may optionally be stored in the target array entry for the first branch. For example, referring to
Referring now to
At step 352, a first branch is predicted taken. For example, referring to
At step 354, a halt counter is set equal to the distance to the second branch. For example, referring to
At step 356, an instruction block may be fetched. For example, referring to
At step 364, the instruction block (fetched at step 356) may be processed without using branch prediction. For example, referring to
Note that, in some embodiments, steps 356, 360, 362, and 364 form a loop that may be repeated for each of multiple instruction blocks while the halt counter is greater than zero. Note also that, because the BPU 170 is gated (i.e., not used) during each of these loops, the electrical energy that would otherwise be required to operate the BPU 170 is reduced or conserved during this period. Accordingly, embodiments may conserve at least some of the power of the battery 135 (shown in
Returning to step 360, if it is determined that the halt counter is not greater than zero, then at step 366, the current instruction block may be processed using branch prediction. For example, referring to
At step 368, the distance value may optionally be updated if the second branch is predicted not taken. For example, referring to
Note that the examples shown in
Referring now to
Although not shown for ease of illustration in
With further reference to
Referring now to
In general, each core 510 may further include low level caches in addition to various execution units and additional processing elements. In turn, the various cores may be coupled to each other and to a shared cache memory formed of a plurality of units of a last level cache (LLC) 540a-540n. In various embodiments, LLC 540 may be shared amongst the cores and the graphics engine, as well as various media processing circuitry. As seen, a ring interconnect 530 thus couples the cores together, and provides interconnection between the cores, graphics domain 520 and system agent circuitry 550. In the embodiment of
As further seen in
Referring to
In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and/or any other element, which is capable of holding a state for a processor, such as an execution state or architectural state. In other words, a processing element, in one embodiment, refers to any hardware capable of being independently associated with code, such as a software thread, operating system, application, or other code. A physical processor typically refers to an integrated circuit, which potentially includes any number of other processing elements, such as cores or hardware threads.
A core often refers to logic located on an integrated circuit capable of maintaining an independent architectural state, wherein each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic located on an integrated circuit capable of maintaining an independent architectural state, wherein the independently maintained architectural states share access to execution resources. As can be seen, when certain resources are shared and others are dedicated to an architectural state, the line between the nomenclature of a hardware thread and core overlaps. Yet often, a core and a hardware thread are viewed by an operating system as individual logical processors, where the operating system is able to individually schedule operations on each logical processor.
Physical processor 1100, as illustrated in
As shown, core 1101 includes two hardware threads 1101a and 1101b, which may also be referred to as hardware thread slots 1101a and 1101b. Therefore, software entities, such as an operating system, in one embodiment potentially view processor 1100 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads concurrently. As alluded to above, a first thread is associated with architecture state registers 1101a, a second thread is associated with architecture state registers 1101b, a third thread may be associated with architecture state registers 1102a, and a fourth thread may be associated with architecture state registers 1102b. Here, each of the architecture state registers (1101a, 1101b, 1102a, and 1102b) may be referred to as processing elements, thread slots, or thread units, as described above.
As illustrated, architecture state registers 1101a are replicated in architecture state registers 1101b, so individual architecture states/contexts are capable of being stored for logical processor 1101a and logical processor 1101b. In core 1101, other smaller resources, such as instruction pointers and renaming logic in allocator and renamer block 1130 may also be replicated for threads 1101a and 1101b. Some resources, such as re-order buffers in reorder/retirement unit 1135, ILTB 1120, load/store buffers, and queues may be shared through partitioning. Other resources, such as general purpose internal registers, page-table base register(s), low-level data-cache and data-TLB 1115, execution unit(s) 1140, and portions of out-of-order unit 1135 are potentially fully shared.
Processor 1100 often includes other resources, which may be fully shared, shared through partitioning, or dedicated by/to processing elements. In
Core 1101 further includes decode module 1125 coupled to fetch unit 1120 to decode fetched elements. Fetch logic, in one embodiment, includes individual sequencers associated with thread slots 1101a, 1101b, respectively. Usually core 1101 is associated with a first ISA, which defines/specifies instructions executable on processor 1100. Often machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode), which references/specifies an instruction or operation to be performed. Decode logic 1125 includes circuitry that recognizes these instructions from their opcodes and passes the decoded instructions on in the pipeline for processing as defined by the first ISA. As a result of the recognition by decoders 1125, the architecture or core 1101 takes specific, predefined actions to perform tasks associated with the appropriate instruction (e.g., the actions shown in
In one example, allocator and renamer block 1130 includes an allocator to reserve resources, such as register files to store instruction processing results. However, threads 1101a and 1101b are potentially capable of out-of-order execution, where allocator and renamer block 1130 also reserves other resources, such as reorder buffers to track instruction results. Unit 1130 may also include a register renamer to rename program/instruction reference registers to other registers internal to processor 1100. Reorder/retirement unit 1135 includes components, such as the reorder buffers mentioned above, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions executed out-of-order.
Scheduler and execution unit(s) block 1140, in one embodiment, includes a scheduler unit to schedule instructions/operation on execution units. For example, a floating point instruction is scheduled on a port of an execution unit that has an available floating point execution unit. Register files associated with the execution units are also included to store information instruction processing results. Exemplary execution units include a floating point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.
Lower level data cache and data translation buffer (D-TLB) 1150 are coupled to execution unit(s) 1140. The data cache is to store recently used/operated on elements, such as data operands, which are potentially held in memory coherency states. The D-TLB is to store recent virtual/linear to physical address translations. As a specific example, a processor may include a page table structure to break physical memory into a plurality of virtual pages.
Here, cores 1101 and 1102 share access to higher-level or further-out cache 1110, which is to cache recently fetched elements. Note that higher-level or further-out refers to cache levels increasing or getting further away from the execution unit(s). In one embodiment, higher-level cache 1110 is a last-level data cache—last cache in the memory hierarchy on processor 1100—such as a second or third level data cache. However, higher level cache 1110 is not so limited, as it may be associated with or includes an instruction cache. A trace cache—a type of instruction cache—instead may be coupled after decoder 1125 to store recently decoded traces.
In the depicted configuration, processor 1100 also includes bus interface module 1105 and a power controller 1160, which may perform power sharing control in accordance with an embodiment of the present invention. Historically, controller 1170 has been included in a computing system external to processor 1100. In this scenario, bus interface 1105 is to communicate with devices external to processor 1100, such as system memory 1175, a chipset (often including a memory controller hub to connect to memory 1175 and an I/O controller hub to connect peripheral devices), a memory controller hub, a northbridge, or other integrated circuit. And in this scenario, bus 1105 may include any known interconnect, such as multi-drop bus, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g. cache coherent) bus, a layered protocol architecture, a differential bus, and a GTL bus.
Memory 1175 may be dedicated to processor 1100 or shared with other devices in a system. Common examples of types of memory 1175 include DRAM, SRAM, non-volatile memory (NV memory), and other known storage devices. Note that device 1180 may include a graphic accelerator, processor or card coupled to a memory controller hub, data storage coupled to an I/O controller hub, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.
Note however, that in the depicted embodiment, the controller 1170 is illustrated as part of processor 1100. Recently, as more logic and devices are being integrated on a single die, such as SOC, each of these devices may be incorporated on processor 1100. For example in one embodiment, memory controller hub 1170 is on the same package and/or die with processor 1100. Here, a portion of the core (an on-core portion) includes one or more controller(s) 1170 for interfacing with other devices such as memory 1175 or a graphics device 1180. The configuration including an interconnect and controllers for interfacing with such devices is often referred to as an on-core (or un-core configuration). As an example, bus interface 1105 includes a ring interconnect with a memory controller for interfacing with memory 1175 and a graphics controller for interfacing with graphics processor 1180. Yet, in the SOC environment, even more devices, such as the network interface, co-processors, memory 1175, graphics processor 1180, and any other known computer devices/interface may be integrated on a single die or integrated circuit to provide small form factor with high functionality and low power consumption.
Embodiments may be implemented in many different system types. Referring now to
Still referring to
Furthermore, chipset 690 includes an interface 692 to couple chipset 690 with a high performance graphics engine 638, by a P-P interconnect 639. In turn, chipset 690 may be coupled to a first bus 616 via an interface 696. As shown in
It should be understood that a processor core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).
Any processor described herein may be a general-purpose processor, such as a Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, XScale™ or StrongARM™ processor, which are available from Intel Corporation, of Santa Clara, Calif. Alternatively, the processor may be from another company, such as ARM Holdings, Ltd, MIPS, etc. The processor may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The processor may be implemented on one or more chips. The processor may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.
It is contemplated that the processors described herein are not limited to any system or device. Other system designs and configurations known in the arts for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand held devices, and various other electronic devices, are also suitable. In general, a huge variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.
Embodiments may be implemented in code and may be stored on a non-transitory storage medium having stored thereon instructions which can be used to program a system to perform the instructions. The storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, solid state drives (SSDs), compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
The following clauses and/or examples pertain to further embodiments. One example embodiment may be a processor including at least one execution unit and prediction gating logic. The prediction gating logic may be to: in response to a first prediction that a first branch is taken, obtain a distance value to a second branch using a target array; and gate a branch prediction unit for a number of instruction blocks equal to the distance value to the second branch. The prediction gating logic may be further to: set a halt counter equal to the distance value; and decrement the halt counter for each of the number of instruction blocks. The branch prediction unit may be to generate a prediction for the second branch when the halt counter is equal to zero. The prediction gating logic may be to determine a preferred component of the branch prediction unit based on the target array, where the branch prediction unit is to generate the prediction for the second branch using the preferred component. The processor may also include a fetch unit to fetch each of the number of instruction blocks. The prediction gating logic may be to obtain the distance value based on a distance portion of a first entry of the target array, wherein the first entry comprises a tag for the first branch. The distance value may be a multiple of a value of the distance portion of the first entry. The processor may also include a decoder to: in response to a second prediction that the first branch is taken, increment a distance counter for each instruction block until a second branch is predicted taken, and store a value of the distance counter in the distance portion of the first entry, where the second prediction occurs prior to the first prediction. The decoder may include a register to store a tag for the first branch.
Another example embodiment may be a system including a processor, and a memory coupled to the processor. The processor may be to: in response to a first prediction that a first branch is taken, obtain a distance value to a second branch using a target array; set a halt counter equal to the distance value; for each instruction block after the first branch, decrement the halt counter, and process the instruction block, without using a branch prediction unit, when the halt counter is greater than zero. The branch prediction unit may be to generate a prediction for a second branch when the halt counter is equal to zero. The branch prediction unit may be to generate the prediction for the second branch processor using a preferred component of the branch prediction unit. The processor may be to identify the preferred component based on a preferred component portion of a first entry of the target array. The processor may be to obtain the distance value by decoding a distance portion of a first entry of the target array, wherein the first entry is associated with the first branch. The processor may be further to, during a training phase: determine, using a distance counter, a number of blocks between the first branch and the second branch; and encode the number of blocks in the distance portion of the first entry of the target array. The processor may be to, during the training phase, encode the number of blocks by removing one or more bits of a bit value of the number of blocks. The processor may be to, during the training phase, store a preferred component identifier in a preferred component portion of the first entry of the target array.
Yet another example embodiment may be a method, including: predicting, by a branch prediction unit of a processor, that a first branch is taken; determining a distance value to a second branch based on a target array; setting a halt counter equal to the distance value; decrementing the halt counter for each instruction block; and gating the branch prediction unit until the halt counter reaches a first value. The method may also include generating a prediction for a second branch when the halt counter reaches the first value. Determining the distance value may include decoding a distance portion of a first entry of the target array. The first entry of the target array may include a tag identifier for the first branch. The method may also include updating the distance portion of the first entry when the second branch is predicted not taken.
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
While the present invention has been described with respect to a limited number of embodiments for the sake of illustration, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
