Breakpointing on register access events or I/O port access events

Abstract

A data processing system 2 is provided with breakpoint circuitry 28 having breakpoint registers 30 which can specify a variety of different types of breakpoint conditions. These breakpoint conditions include register access breakpoints which are triggered when an access is made to either a general purpose register 8 or a configuration register 22, 24. The breakpoints can also include input/output port access breakpoints which are triggered when an access is made to a predetermined one of a plurality of input/output ports 26 by an appropriate program instruction or in another way.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically illustrates a data processing apparatus including breakpointing mechanisms;

FIG. 2 schematically illustrates debug registers of various types within a breakpointing mechanism;

FIG. 3 is a flow diagram schematically illustrating the behaviour of the breakpointing mechanisms when performing register breakpointing;

FIG. 4 is a flow diagram schematically illustrating the behaviour of the breakpointing mechanisms when performing I/O port breakpointing; and

FIG. 5 is a logic diagram illustrating combinatorial logic which can be used to implement the register breakpointing of FIG. 3.

Claims

1. Apparatus for processing data, said apparatus comprising: one or more registers; andbreakpoint circuitry responsive to an access to at least one of said one or more registers to trigger a breakpoint response.

2. Apparatus as claimed in claim 1, wherein said one or more registers include one or more general purpose registers storing data values to be manipulated.

3. Apparatus as claimed in claim 1, wherein said one or more registers include one or more control registers storing control values controlling configuration of said apparatus.

4. Apparatus as claimed in claim 1, wherein said breakpoint circuitry comprises one or more debug registers, said breakpoint circuitry being responsive to register access characterising data held within respective debug registers to determine characteristics of accesses to a target register of said one or more registers that trigger said breakpoint response.

5. Apparatus as claimed in claim 4, wherein said register access characterising data comprises an identifier of said target register for which register accesses are monitored by said breakpoint circuitry.

6. Apparatus as claimed in claim 4, wherein said register access characterising data comprises an identifier of one or more types of access to said target register for which register accesses are monitored by said breakpoint circuitry.

7. Apparatus as claimed in claim 6, wherein said one or more types of access includes one or more of: a read access;a write accessa reset; andany access.

8. Apparatus as claimed in claim 4, wherein said register access characterising data comprises a mask value specifying one or more bits within said target register for which register accesses are monitored by said breakpoint circuitry.

9. Apparatus as claimed in claim 4, wherein said register access characterising data comprises an identifier of a breakpoint handler for said target register for which register accesses are monitored by said breakpoint circuitry, said breakpoint handler being invoked when an access being monitored is made to said target register.

10. Apparatus as claimed in claim 9, wherein said identifier of a breakpoint handler specifies a memory address of breakpoint handling code to be invoked if said access being monitored is made to said target register.

11. Apparatus as claimed in claim 4, wherein said one or more debug registers include a mode bit controlling whether said debug register is used by said breakpoint circuitry to specify characteristics of an access to said target register to trigger said breakpoint response or characteristics of a memory access to trigger said breakpoint response.

12. Apparatus for processing data, said apparatus comprising: one or more input/output ports; andbreakpoint circuitry responsive to an access to at least one of said one or more input/output ports to trigger a breakpoint response.

13. Apparatus as claimed in claim 12, wherein said breakpoint circuitry comprises one or more debug registers, said breakpoint circuitry being responsive to input/output port access characterising data held within respective debug registers to determine characteristics of accesses to a target input/output port of said one or more input/output ports that trigger said breakpoint response.

14. Apparatus as claimed in claim 13, wherein said input/output port access characterising data comprises an identifier of said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry.

15. Apparatus as claimed in claim 13, wherein said input/output port access characterising data comprises an identifier of one or more types of access to said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry.

16. Apparatus as claimed in claim 15 wherein said one or more types of access includes one or more of: a read access;a write access; andany access.

17. Apparatus as claimed in claim 13, wherein said input/output port access characterising data comprises an mask value specifying one or more bits within said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry.

18. Apparatus as claimed in claim 13, wherein said input/output port access characterising data comprises an identifier of a breakpoint handler for said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry, said breakpoint handler being invoked when an access being monitored is made to said target input/output port.

19. Apparatus as claimed in claim 18, wherein said identifier of a breakpoint handler specifies a memory address of breakpoint handling code to be invoked said access being monitored is made to said target input/output port.

20. Apparatus as claimed in claim 13, wherein said one or more debug registers include a mode bit controlling whether said debug register is used by said breakpoint circuitry to specify characteristics of an access to a said target input/output port to trigger said breakpoint response or characteristics of a memory access to trigger said breakpoint response.

21. Apparatus for processing data, said apparatus comprising: one or more register means; andbreakpoint means for responding to an access to at least one of said one or more register means to trigger a breakpoint response.

22. Apparatus for processing data, said apparatus comprising: one or more input/output port means; andbreakpoint means for responding to an access to at least one of said one or more input/output port means to trigger a breakpoint response.

23. A method of triggering a breakpoint response within an apparatus for processing data having one or more registers, said method comprising the steps of: detecting with breakpoint circuitry an access to at least one of said one or more registers; andin response to detecting said access, triggering said breakpoint response.

24. A method as claimed in claim 23, wherein said one or more registers include one or more general purpose registers storing data values to be manipulated.

25. A method as claimed in claim 23, wherein said one or more registers include one or more control registers storing control values controlling configuration of said apparatus for processing data.

26. A method as claimed in claim 23, comprising storing register access characterising data within respective debug registers of one or more debug registers of said breakpoint circuitry to determine characteristics of accesses to a target register of said one or more registers that trigger said breakpoint response.

27. A method as claimed in claim 26, wherein said register access characterising data comprises an identifier of said target register for which register accesses are monitored by said breakpoint circuitry.

28. A method as claimed in claim 26, wherein said register access characterising data comprises an identifier of one or more types of access to said target register for which register accesses are monitored by said breakpoint circuitry.

29. A method as claimed in claim 28, wherein said one or more types of access includes one or more of: a read access;a write accessa reset; andany access.

30. A method as claimed in claim 26, wherein said register access characterising data comprises a mask value specifying one or more bits within said target register for which register accesses are monitored by said breakpoint circuitry.

31. A method as claimed in claim 26, wherein said register access characterising data comprises an identifier of a breakpoint handler for said target register for which register accesses are monitored by said breakpoint circuitry, said breakpoint handler being invoked when an access being monitored is made to said target register.

32. A method as claimed in claim 31, wherein said identifier of a breakpoint handler specifies a memory address of breakpoint handling code to be invoked if said access being monitored is made to said target register.

33. A method as claimed in claim 26, wherein said one or more debug registers store a mode bit controlling whether said debug register is used by said breakpoint circuitry to specify characteristics of an access to said target register to trigger said breakpoint response or characteristics of a memory access to trigger said breakpoint response.

34. A method of triggering a breakpoint response within an apparatus for processing data having one or more input/output ports, said method comprising the steps of: detecting with breakpoint circuitry an access to at least one of said one or more input/output ports; andin response to detecting said access, triggering said breakpoint response.

35. A method as claimed in claim 34, comprising storing input/output port access characterising data within respective debug registers of one or more debug registers of said breakpoint circuitry to determine characteristics of accesses to a target input/output port of said one or more input/output ports that trigger said breakpoint response.

36. A method as claimed in claim 35, wherein said input/output port access characterising data comprises an identifier of said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry.

37. A method as claimed in claim 35, wherein said input/output port access characterising data comprises an identifier of one or more types of access to said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry.

38. A method as claimed in claim 37, wherein said one or more types of access includes one or more of: a read access;a write accessa reset; andany access.

39. A method as claimed in claim 35, wherein said input/output port access characterising data comprises a mask value specifying one or more bits within said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry.

40. A method as claimed in claim 35, wherein said input/output port access characterising data comprises an identifier of a breakpoint handler for said target input/output port for which input/output port accesses are monitored by said breakpoint circuitry, said breakpoint handler being invoked when an access being monitored is made to said target input/output port.

41. A method as claimed in claim 40, wherein said identifier of a breakpoint handler specifies a memory address of breakpoint handling code to be invoked if said access being monitored is made to said target input/output port.

42. A method as claimed in claim 35, wherein said one or more debug registers store a mode bit controlling whether said debug register is used by said breakpoint circuitry to specify characteristics of an access to said target input/output port to trigger said breakpoint response or characteristics of a memory access to trigger said breakpoint response.