The subject matter herein generally relates to a brightness adjusting circuit.
The brightness of display will remain when the brightness of the environment around the display changes, which is uncomfortable for users.
Implementations of the present technology will now be described, by way of example only, with reference to the attached figure.
It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein can be practiced without these specific details. In other instances, methods, procedures and components have not been described in detail so as not to obscure the related relevant feature being described. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features. The description is not to be considered as limiting the scope of the embodiments described herein.
Several definitions that apply throughout this disclosure will now be presented.
The term “coupled” is defined as connected, whether directly or indirectly through intervening components, and is not necessarily limited to physical connections. The connection can be such that the objects are permanently connected or releasably connected. The term “comprising” means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in a so-described combination, group, series and the like.
The present disclosure is in relation to a brightness adjusting circuit.
The acquisition module 10 can comprise resistors R1, R2 and a capacitor C1. A first terminal of the capacitor C1 is coupled to a power supply P3V3. The first terminal of the capacitor C1 is also coupled to ground through the resistors R1 and R2 in that order. A second terminal of the capacitor C1 is coupled to ground. A node between the resistors R1 and R2 is coupled to the conversion module 20.
The conversion module 20 can comprise an analog-digital converter U1, a crystal oscillator Y1, a resistor R3, and capacitors C2-C6. An input pin VIN of the analog-digital converter U1 is coupled to the node between the resistors R1 and R2. A clock pin CLK of the analog-digital converter U1 is coupled to ground through the crystal oscillator Y1 and the capacitor C2 in that order. The clock pin CLK of the analog-digital converter U1 is also coupled to ground through the capacitor C3. A power pin VCC of the analog-digital converter U1 is coupled to the power supply P3V3. The power pin VCC of the analog-digital converter U1 is also coupled to ground through the capacitor C4. A selection pin CS of the analog-digital converter U1 is coupled to ground through the resistor R3 and the capacitor C5 in parallel. The selection pin CS of the analog-digital converter U1 is also coupled to the control module 30. An output pin DOUT of the analog-digital converter U1 is coupled to ground through the capacitor C6. The output pin DOUT of the analog-digital converter U1 is also coupled to the control module 30 and the processing module 40.
The control module 30 can comprise a single-chip U2, capacitors C7, C8, a resistor R4, a crystal oscillator Y2, and a switch SW1. A power pin VPP of the single-chip U2 is coupled to a power supply PSV. A first pin PO of the single-chip U2 is coupled to the selection pin CS of the analog-digital converter U1. A first clock pin XTAL1 of the single-chip U2 is coupled to a second clock pin XTAL2 of the single-chip U2 through the crystal oscillator Y2. The first clock pin XTAL1 of the single-chip U2 is also coupled to ground through the capacitor C7. The second clock pin XTAL1 of the single-chip U2 is also coupled to ground through the capacitor C8. A reset pin RST of the single-chip U2 is coupled to the power supply P5V through the switch SW1. The reset pin RST of the single-chip U2 is also coupled to ground through the resistor R4. A fourth pin P3 of the single-chip U2 is coupled to the manual controller 50. A second pin P1, a third pin P2, and a fifth pin P4 of the single-chip U2 are coupled to the processing module 40. An input pin RXD of the single-chip U2 is coupled to the output pin DOUT of the analog-digital converter U1.
The processing module 40 can comprise a timer U3, an electronic switch Q1, an inductor L1, four resistors R5-R8, and three capacitors C9-C11. A clock pin TRG of the timer U3 is coupled to the third pin P2 of the single-chip U2. A reset pin RST of the timer U3 is coupled to the second pin P1 of the single-chip U2. The reset pin RST of the timer U3 is also coupled to ground through the resistor R6. A modulation pin CV of the timer U3 is coupled to the output pin DOUT of the analog-digital converter U1 through the resistor R7. The modulation pin CV of the timer U3 is also coupled to ground through the capacitor C10. A power pin VCC of the timer U3 is coupled to the power supply PSV. The power pin VCC of the timer U3 is also coupled to a first terminal of the electronic switch Q1. A second terminal of the electronic switch Q1 is coupled to ground. A control terminal of the electronic switch Q1 is coupled to the fifth pin P4 of the single-chip U2. A lock pin THR of the timer U3 is coupled to the power pin VCC of the timer U3 through the resistor R5. The lock pin THR of the timer U3 is also coupled to ground through the capacitor C11. A discharge pin D of the timer U3 is also coupled to the lock pin THR of the timer U3. An output pin OUT of the timer U3 is coupled to the manual controller 50 through the inductor L1. The output pin OUT of the timer U3 is also coupled to ground through the resistor R8. The output pin OUT of the timer U3 is also coupled to ground through the inductor L1 and the capacitor C9 in that order.
The manual controller 50 can comprise an operation unit 300 and two diodes D1, D2. An output terminal a of the operation unit 300 is coupled to the fourth pin P3 of the single-chip U2. The output terminal a of the operation unit 300 is also coupled to an anode of the diode D1. A cathode terminal of the diode D1 is coupled to an input terminal A of the display 200. An input terminal b of the operation unit 300 is coupled to an anode of the diode D2. A cathode terminal of the diode D2 is coupled to an output terminal B of the display 200. The input terminal A of the display 200 is also coupled to the output pin OUT of the timer U3 through the inductor L1.
In at least one embodiment, the resistor R1 is a photoresistor. A resistance of the resistor R1 changes according to the brightness of environment.
When the selection pin CS of the analog-digital converter U1 receives a high level signal, such as logic 1, the analog-digital converter U1 stops working. The analog-digital converter U1 operates when the selection pin CS of the analog-digital converter U1 does not received any signal. When the reset pin RST of the timer U3 receives a high level signal, the timer U3 is reset. The fifth pin P4 of the single-chip U2 outputs a high level signal when the fourth pin P3 receives any signal.
When the brightness adjusting circuit works, the resistance of the resistor R1 changes according to the brightness of environment. Waveform of analog signals received by the input pin VIN of the analog-digital converter U1 is similar to the
The input terminal A of the display 200 receives manual signals when someone manual controls the operation unit 300 to adjust the brightness grade of the display 200. The fifth pin P4 of the single-chip U2 outputs a high level signal when the fourth pin P3 of the single-chip U2 receives the manual signals. The electronic switch Q1 is turned off. The power supply P5V stops supplying power to the timer U3 and the timer U3 stops working. The first pin PO of the single-chip U2 outputs a high level signal and the analog-digital converter U1 stops working. The display 200 stops receiving the brightness signals and receives the manual signals to adjust the brightness of the display 200.
When the input terminal A of the display 200 dose not receive the manual signals, connected the power supply P5V and the reset pin RST of the single-chip U2, through the switch SW1, to reset the single-chip U2, and then disconnected the power supply P5V from the reset pin RST of the single-chip U2. The first pin PO of the single-chip U2 stops outputting the high level signal the analog-digital converter U1 turns back to work. The fifth pin P4 of the single-chip U2 stops outputting the high level signal and the power supply P5V turns back to supply power to the timer U3. The second pin P1 of the single-chip U2 outputs a high level signal to the reset pin RST of the timer U3 to reset the timer U3. The display 200 turns back to receive the brightness signals to adjust the brightness of the display 200.
In at least one embodiment, the electronic switch Q1 is an n-channel field effect transistor.
The embodiments shown and described above are only examples. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, including in matters of shape, size and arrangement of the parts within the principles of the present disclosure up to, and including, the full extent established by the broad general meaning of the terms used in the claims.
Number | Date | Country | Kind |
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201310367235X | Aug 2013 | CN | national |