The invention relates to control circuits, and more particularly, to brightness control circuits employed in display devices.
However, complexity and occupied area of the entire driver are increased due to the brightness control circuit 10 at least requiring the sample and hold circuit 55, the current source 72 and the comparator 75. Further, the brightness control circuit 10 has a slower operating speed, and thus, is not suitable for large size and high resolution display devices. Furthermore, the pulse width modulated signal of the control circuit 10 is not precise due to charge sharing and clock feedthrough in the sample and hold circuit 55.
In a brightness control circuit, a current digital-to-analog converter (DAC) receives a digital code and generates a control current, and a one-shot circuit is coupled to the current DAC to generate a pulse width modulated (PWM) signal according to the control current and a clock signal. The digital code and pulse width modulated signal have an exponential relationship.
In an embodiment of a brightness control circuit, the one-shot circuit includes a delay circuit coupled to the current DAC, delaying the clock signal for a predetermined time interval and outputting a delayed clock signal according to the control current; and a logic gate unit coupled to the delay unit, generating the pulse width modulated signal according to the clock signal and the delayed clock signal. The pulse width of the pulse width modulated signal depends on the predetermined time interval.
The invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein:
FIGS. 4A˜4C show different wave diagrams of brightness control circuit with different digital codes according to the first embodiment;
FIGS. 10A˜10C show different wave diagrams of a brightness control circuit with different digital codes according to the second embodiment; and
FIGS. 11A˜11C show different wave diagrams of brightness control circuit with different digital codes according to the fourth embodiment.
For example, the one-shot circuit can be a pulse width modulator, and can comprise a delay circuit 122 and a logic gate unit 124. The delay circuit 122 receives the output current CTO from the current DAC 110 and an external clock signal CLK, delays the clock signal CLK for a predetermined time interval according to the output current CTO, and outputs a delayed clock signal DCLK (delay signal). Namely, the delay circuit 122 generates different time delays between the clock signal CLK and the delayed signal DCLK according to different output currents CTO. The logic gate unit 124 receives the clock signal CLK and the delayed signal DCLK and generates a pulse width modulated signal PWM_out to output to a corresponding pixel of a display device, thereby controlling brightness. Namely, the logic gate unit 124 generates pulse width modulated signal PWM_out with different pulse widths according to different time delays between the clock signal CLK and the delayed signal DCLK.
The delay circuit 122 comprises four current-controlled current sources I1˜I4 and two delay stages D1 and D2, delaying the clock signal CLK for a predetermined time interval according to the output current CTO and outputting a delayed signal DCLK (delayed clock signal). The delay stage D1 comprises transistors T9 and T10 and has an input terminal coupled to the clock signal CLK, and the delay stage D2 comprises transistors T11 and T12, an input terminal coupled to the output terminal of the delay stage D1 and an output terminal outputting the delayed signal DCLK. The current-controlled current source 11 is coupled between the power terminal VDD and the source terminal of the transistor T9, and the current-controlled current source 12 is coupled between the power terminal VDD and the source terminal of the transistor T10. The current-controlled current source 13 is coupled between the power terminal VDD and the source terminal of the transistor T11, and the current-controlled current source 14 is coupled between the power terminal VDD and the source terminal of the transistor T12. The control terminals of the current-controlled current source I1˜I4 are coupled to the output current CTO from the current DAC 110. The current-controlled current sources I1˜I4 charges/discharges the delay stages D1 and D2 according to the output current CTO, thereby controlling the delay stage D2 to output the delayed clock signal DCLK. Thus, there is a time delay between the clock signal CLK and the delayed clock signal DCLK (delay signal).
The logic gate unit 124 comprises an inverter INV3 and a AND gate AND1, generating a corresponding pulse width modulated signal PWN_out according to the clock signal CLK and the delayed clock signal DCLK. The clock signal CLK is coupled to the input terminal IT1 of the AND gate AND1 and the delayed clock signal DCLK is coupled to the other input terminal IT2 of the AND gate AND1. Due to the time delay between the clock signals CLK and DCLK, the AND gate AND1 generates a pulse width modulated signal PWM_out to a corresponding pixel of a display device thereby controlling brightness. In this embodiment, the pulse width of the pulse width modulated signal PWM_out is determined by the time delay between the clock signal CLK from an external timing controller and the delayed clock signal DCLK from the delay circuit 122.
FIGS. 4A˜4C show different wave diagrams of brightness control circuits with different digital codes.
For example, the current DAC 110 generates the output currents CTO_01, CTO_10 and CTO_11 when the digital code (C1, C0) is “01”, “10 and “11” respectively. In this embodiment, CTO_01<CTO_10<CTO_11, larger output current CTO and the time delay between the clock signal CLK and the delayed clock signal DCLK is smaller. Namely, the delay circuit 122 outputs the delayed clock signal DCLK with the larger output current CTO more rapidly. As shown in FIGS. 4A˜4C, the delay circuit 122 delays the clock signal CLK for time intervals dt1, dt2 and dt3 respectively, according to the output currents CTO_01, CTO_10 and CTO_11. The delay time intervals are dt1>dt2>dt3 because the output currents are CTO_01<CTO_10<CTO_11.
If the clock signal CLK is high before time t0, the input terminals IT1 and IT2 of the AND gate AND1 are at low and high levels respectively, such that the output terminal of the AND gate AND1 is maintained at a low level. The clock signal CLK goes low when time is t1, the input terminal IT1 is at a high level. At this time, due to the delay circuit 122, the input terminal IT2 is still maintained at the high level, and thus, the output terminal of the AND gate AND1 is changed to a high level.
When the clock signal CLK is delayed for a time interval, such as time t1, t2 or t3, the delayed clock signal DCLK is output to the input terminal IT2, namely the input terminal IT2 is changed to a low level. At this time, the output terminal of the AND gate AND1 is changed to a low level accordingly. As shown in FIGS. 4A˜4C, pulse widths of the pulse width modulated signal PWM_out1˜PWM_out3 are essentially equal to the corresponding delay time intervals dt1, dt2 and dt3 respectively. Further, the current of the second differential pair (T5 and T6) can be designed to be two times that of the first differential pair (T1 and T2), such that delay time intervals dt1:dt2:dt3=1:2:3, and thus, the pulse widths PW3: PW2: PW1=1:2:3 can be obtained. Thus, there is an inverse proportion between a digital value DV represented by a digital code DIC and the pulse width PW, as shown in
FIGS. 10A˜10C show different wave diagrams of brightness control circuit with different digital codes.
For example, the current DAC 110 generates the output currents CTO_01, CTO_10 and CTO_11 when the digital code (C1, C0) is “01”, “10 and “11” respectively. In this embodiment, CTO_01<CTO_10<CTO_11, larger output current CTO and the time delay between the clock signal CLK and the delayed clock signal DCLK is smaller. Namely, the delay circuit 122 outputs the delayed clock signal DCLK with the larger output current CTO more rapidly. As shown in FIGS. 10A˜10C, the delay circuit 122 delays the clock signal CLK for time intervals dt1, dt2 and dt3 respectively, according to the output currents CTO_01, CTO_10 and CTO_11. The delay time intervals are dt1>dt2>dt3 because of output currents are CTO_01<CTO_10<CTO_11.
If the clock signal CLK is low before time t0, the input terminals IT1 and IT2 of the AND gate AND1 are at low and high levels respectively, such that the output terminal of the AND gate AND1 is maintained at a low level. The clock signal CLK goes high when time is t1, the input terminal IT1 is at a high level. At this time, due to the delay circuit 122, the input terminal IT2 is still maintained at the high level, and thus, the output terminal of the AND gate AND1 is changed to a high level.
When the clock signal CLK is delayed for a time interval, such as time t1, t2 or t3, the delayed clock signal DCLK is output to the input terminal IT2, namely the input terminal IT2 is changed to a low level. At this time, the output terminal of the AND gate AND1 is changed to a low level accordingly. As shown in FIGS. 10A˜10C, pulse widths of the pulse width modulated signal PWM_out1˜PWM_out3 are essentially equal to the corresponding delay time intervals dt1, dt2 and dt3 respectively. Further, the current of the second differential pair (T5 and T6) can be designed to be two times that of the first differential pair (T1 and T2), such that delay time intervals dt1:dt2:dt3=1:2:3, and thus, the pulse widths PW3:PW2:PW1=1:2:3 can be obtained. Thus, there is an inverse proportion between a digital value DV represented by a digital code DIC and the pulse width PW, as shown in
FIGS. 11A˜11C show different wave diagrams of brightness control circuit with different digital codes.
For example, the current DAC 110 generates the output currents CTO_01, CTO_10 and CTO_11 when the digital code (C1, C0) is “01”, “10 and “11” respectively. In this embodiment, CTO_01<CTO_10<CTO_11, larger output current CTO and the time delay between the clock signal CLK and the delayed clock signal DCLK is smaller. Namely, the delay circuit 122 outputs the delayed clock signal DCLK with the larger output current CTO more rapidly. As shown in FIGS. 11A˜11C, the delay circuit 122 delays the clock signal CLK for time intervals dt1, dt2 and dt3 respectively, according to the output currents CTO_01, CTO_10 and CTO_11. The delay time intervals are dt1>dt2>dt3 because of output currents are CTO_01<CTO_10<CTO_11.
If the clock signal CLK is low before time t0, the input terminals IT1 and IT2 of the AND gate AND1 are at low level both, such that the output terminal of the AND gate AND1 is maintained at a low level. The clock signal CLK goes high when time is t1, the input terminal IT1 is at a high level. At this time, due to the delay circuit 122, the input terminal IT2 is still maintained at the low level, and thus, the output terminal of the AND gate AND1 is maintained at the low level also.
When the clock signal CLK is delayed for a time interval, such as time t1, t2 or t3, the delayed clock signal DCLK is output to the input terminal IT2, namely the input terminal IT2 is changed to a high level. At this time, the output terminal of the AND gate AND1 is changed to a high level accordingly. When the time is t1′, t2′ or t3′, the clock signal CLK goes low and the input terminal IT1 is changed to a low level. At this time, the output terminal of the AND gate AND1 is changed to a low level accordingly.
As shown in FIGS. 11A˜11C, pulse widths of the pulse width modulated signal PWM_outl_PWM_out3 are essentially equal to the corresponding delay time intervals dt1, dt2 and dt3 respectively. Further, the current of the second differential pair (T5 and T6) can be designed to be two times that of the first differential pair (T1 and T2), such that delay time intervals dt1:dt2:dt3=1:2:3, and thus, the pulse widths PW1:PW2:PW3=1:2:3 can be obtained. Thus, there is a direct proportion between a digital value DV represented by a digital code DIC and the pulse width PW, as shown in
Thus, the brightness control circuits 100A˜100F can generate PWM signals with different pulse widths according to different digital codes DIC from the external timing controller (not shown). Further, the invention does not need to a latch voltage value by a sample and hold circuit for conversion to a pulse width modulated signal, and thus the invention has a higher speed and is suitable for large size and high resolution display devices. Furthermore, because the brightness control circuits 100A˜100F do not require a sample and hold circuit, incorrect pulse width modulated signals caused by charge sharing and clock feedthrough is prevented.
However, human eyes will produce an integration effect due to brightness generated by the time intervals. Namely, for human eyes, there is a non-linear relationship between the pulse width PW and the brightness B as shown in
In view of this, by modifying the size of the elements, such as transistors T9˜T14 or current source I1˜I6, in the delay circuit 122, the brightness control circuit 100A˜100F can obtain an exponential relationship between the digital value DV represented by a digital code DIC and the delay time interval of the delayed clock signal DCLK by the delay circuit 122. Because pulse widths of the pulse width modulated signal are essentially equal to the corresponding delay time interval of the delayed clock signal, there is also an exponential relationship between the digital value DV represented by a digital code DIC and the pulse width of the corresponding pulse width modulated signal, as shown in
The timing controller 220 outputs the digital code DIC and scan signal HSX to the data driver 230 and the scan signal VSX to the scan driver 240. The data driver 230 comprises N brightness control circuits 100_1˜100_N as shown in FIGS. 2A˜2B or 3A˜3D, converting the digital code DIC from the timing controller 220 to corresponding pulse width modulated signals to output to the buffer stage 232. For example, each brightness control circuit converts a digital code of N bits to a corresponding pulse width modulated signal and outputs to the buffer stage 232. The scan driver 240 drives the display panel 250 to control brightness of pixels thereof according to the pulse width modulated signal from the buffer stage 232. The display panel can be a plasma display panel, an organic light emitting diode (OLED) display panel or the like.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Number | Date | Country | Kind |
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93127845 | Sep 2004 | TW | national |