Claims
- 1. A differential amplifier, comprising:
- (a) first and second field effect transistors, the sources of said transistors electrically connected;
- (b) first and second inputs electrically connected to the gates of said first and second transistors, respectively;
- (c) a first current source electrically connected from said first transistor source to said first input;
- (d) a second current source electrically connected from said second transistor source to said second input; and
- (e) first and second outputs connected to the drains of said first and second transistors, respectively.
- 2. The amplifier of claim 1, further comprising:
- (a) level shifting diodes between said first input and said first transistor gate and between said second input and said second transistor gate.
- 3. The amplifier of claim 2, wherein:
- (a) said current sources are zero-biased field effect transistors.
- 4. The amplifier of claim 1, wherein:
- (a) said current sources are inductors.
- 5. The amplifier of claim 1, wherein:
- (a) said first and second field effect transistors are both dual gate field effect transistors with the second gate of said first field effect transistor connected to the second gate of said second field effect transistor.
- 6. The amplifier of claim 1, wherein:
- (a) said field effect transistors are all MESFETs with gallium arsenide semiconductor.
- 7. The amplifier of claim 1, further comprising:
- (a) a push-pull single-ended output stage with inputs connected to said first and second outputs.
- 8. The amplifier of claim 7, wherein:
- (a) said push-pull stage includes third and fourth field effect transistors connected in series and with at least one of the gates of said third and fourth transistors level shifted to form said stage inputs.
- 9. A broadband differential amplifier, comprising:
- (a) first and second input terminals, each of said terminals with a predetermined first dc potential;
- (b) an output terminal;
- (c) a first differential amplifying circuit including first and second MESFETs, the gates of said first and second MESFETs connected through level shifters to said first and second input terminals, respectively, and the sources of said MESFETs connected together;
- (d) a first current source connected between the source of said first MESFET and said first input;
- (e) a second current source connected between the source of said second MESFET and said second input; and
- (f) a load circuit for said MESFETs and connected from the drains of said MESFETs to said output terminal.
- 10. The amplifier of claim 9, wherein:
- (a) said load circuit includes third and fourth MESFETs push-pull connected with the gates of said third and fourth MESFETs connected through at least one level shifter to the drains of said first and second MESFETs, respectively.
- 11. The amplifier of claim 10, wherein:
- (a) said first and second MESFETs are each dual gate MESFETs with the second gates connected together and connected through a level shifter to the sources of said first and second MESFETs.
- 12. The amplifier of claim 10, wherein:
- (a) said MESFETs, load circuit, and level shifters are made of gallium arsenide and metal.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation-in-part of copending U.S. application Ser. No. 855,546, filed Apr. 23, 1986. The cross-referenced application is assigned to the assignee of this application.
Non-Patent Literature Citations (1)
Entry |
Wyland, "FET Cascode Technique Optimizes Differential Amplifier Performances", Electronics, Jan. 18, 1971, pp. 81-84. |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
855546 |
Apr 1986 |
|