Patent Application
20240097328
This application claims priority to Korean Patent Application No. 10-2022-0116379, filed on Sep. 15, 2022, with the Korean Intellectual Property Office (KIPO), the entire contents of which are hereby incorporated by reference.
Exemplary embodiments of the present disclosure relate to a wideband planar array antenna having circular polarization, and more specifically, to a broadband feed network device for realizing low axial ratio characteristics and a planar array antenna using the same.
In the conventional planar array antenna technology with circular polarization, a plurality of different feed networks are generally used for a planar array antenna operating in a narrowband or multiple bands.
Further, when a planar array antenna operating in a wideband is designed, it is possible to design unit radiating elements in a wideband, but in designing of a feed network, it is difficult to implement excellent axial ratio characteristics in a wideband because a large phase dispersion error according to a change in frequency occurs.
Accordingly, in the conventional planar array antenna technology, a method capable of implementing low axial ratio characteristics in a wideband is required.
Accordingly, exemplary embodiments of the present disclosure are provided to substantially obviate one or more problems due to limitations and disadvantages of the related art.
Exemplary embodiments of the present disclosure are derived to meet the above-described needs of the conventional planar array antenna technology, which provide a planar array antenna having circular polarization with low axial ratio characteristics in a wideband by introducing a circuit network that corrects a frequency-phase dispersion error generated when a feed network for implementing circular polarization is designed in a wideband.
Exemplary embodiments of the present disclosure also provide a feed network device capable of correcting a frequency-phase dispersion error in order to implement low axial ratio characteristics in a wideband planar array antenna.
According to a first exemplary embodiment of the present disclosure, a feed network device, which is electrically connected to unit radiating elements for circular polarization, may comprise a phase offset compensation circuit configured to correct a phase dispersion error according to a change in frequency so that four quarter arrays obtained by vertically and horizontally dividing a planar array of the unit radiating elements symmetrically are electrically and rotatably sequentially disposed clockwise or counterclockwise.
The phase offset compensation circuit may include a 180° phase offset compensation circuit, and two 90° phase delay compensation circuits coupled to both ends of the 180° phase offset compensation circuit.
The 180° phase offset compensation circuit may include a standard transmission line with a 360° electrical length, a main line with a 180° electrical length, and open-short stub lines coupled to both ends of the main line and having a 45° electrical length, wherein a characteristic impedance of the main line and characteristic impedances of the open-short stub lines are adjusted to adjust a slope of the phase dispersion error according to a change in frequency of a transmission line.
Each of the two 90° phase delay compensation circuits may include a standard transmission line with a 270° electrical length, a main line with a 180° electrical length, and open-short stub lines coupled to both ends of the main line and having a 45° electrical length, wherein a characteristic impedance of the main line and characteristic impedances of the open-short stub lines are adjusted to adjust a slope of the phase dispersion error according to a change in frequency of the transmission line.
Each of the two 90° phase delay compensation circuits may be configured to provide two output power feeds having the same transmission amplitude and a 90° phase difference characteristic.
Electrical characteristics of the four output power feeds provided by the two 90° phase delay compensation circuits may be configured so that the quarter arrays are rotatably sequentially disposed clockwise or counterclockwise by 90°.
The feed network device may further comprise four power distribution circuits coupled to the two 90° phase delay compensation circuits.
Among the four power distribution circuits, a first power distribution circuit and a second power distribution circuit may be connected to one side and the other side of the 90° phase delay compensation circuit positioned on one side of the 180° phase offset compensation circuit, respectively, and may disposed to supply power to each of two quarter arrays of the four quarter arrays, and among the four power distribution circuits, a third power distribution circuit and a fourth power distribution circuit may be connected to one side and the other side of the 90° phase delay compensation circuit positioned on the other side of the 180° phase offset compensation circuit, respectively, and may be disposed to supply power to each of remaining two quarter arrays of the four quarter arrays.
The four quarter arrays may include a first ring array disposed at an inner center of a planar array having a circular structure, a second ring array disposed around the first ring array, and a third ring array which is spaced a predetermined interval from the second ring array and disposed on an outer edge of the planar array, wherein the four power distribution circuits are controlled so that the first ring array and the second ring array have the same phase and the third ring array has a phase opposite thereto.
The feed network device may further comprise a control device configured to control operations of the four power distribution circuits.
According to a second exemplary embodiment of the present disclosure, a planar array antenna may comprise: unit radiating elements configured to constitute a planar array and generate circular polarization; and a feed network device which is electrically connected to the unit radiating elements, wherein the feed network device includes a phase offset compensation circuit that corrects a phase dispersion error according to a change in frequency so that four quarter arrays obtained by symmetrically vertically and horizontally dividing the planar array symmetrically are electrically and rotatably sequentially disposed clockwise or counterclockwise.
The phase offset compensation circuit may include a 180° phase offset compensation circuit, and two 90° phase delay compensation circuits coupled to both ends of the 180° phase offset compensation circuit.
The 180° phase offset compensation circuit may include a standard transmission line with a 360° electrical length, a main line with a 180° electrical length, and open-short stub lines coupled to both ends of the main line and having a 45° electrical length, wherein a characteristic impedance of the main line and characteristic impedances of the open-short stub lines are adjusted to adjust a slope of the phase dispersion error according to a change in frequency of a transmission line.
Each of the two 90° phase delay compensation circuits may include a standard transmission line with a 270° electrical length, a main line with a 180° electrical length; and open-short stub lines coupled to both ends of the main line and having a 45° electrical length, wherein a characteristic impedance of the main line and characteristic impedances of the open-short stub line are adjusted to adjust a slope of the phase dispersion error according to a change in frequency of the transmission line.
Each of the two 90° phase delay compensation circuits may provide two output power feeds with the same transmission amplitude and characteristic of a 90° phase difference.
Electrical characteristics of the four output power feeds provided by the two 90° phase delay compensation circuits may be configured so that the quarter arrays are rotatably sequentially disposed clockwise or counterclockwise by 90°.
The feed network device may further include four power distribution circuits coupled to the two 90° phase delay compensation circuits.
Among the four power distribution circuits, a first power distribution circuit and a second power distribution circuit may be connected to one side and the other side of the 90° phase delay compensation circuit positioned on one side of the 180° phase offset compensation circuit, respectively, and may be disposed to supply power to each of two quarter arrays of the four quarter arrays, and among the four power distribution circuits, a third power distribution circuit and a fourth power distribution circuit may be connected to one side and the other side of the 90° phase delay compensation circuit positioned on the other side of the 180° phase offset compensation circuit, respectively, and may be disposed to supply power to each of remaining two quarter arrays of the four quarter arrays.
The four quarter arrays may include a first ring array disposed at an inner center of a planar array having a circular structure, a second ring array disposed around the first ring array, and a third ring array which is spaced a predetermined interval from the second ring array and disposed on an outer edge of the planar array, wherein the four power distribution circuits are controlled so that the first ring array and the second ring array have the same phase and the third ring array has a phase opposite thereto.
The planar array antenna may further comprise a control device configured to control operations of the four power distribution circuits.
According to the present disclosure, in order to correct a frequency-phase dispersion error in a feed network of a planar array antenna, by placing open-short stub lines having a 45° electrical length on both ends of a main line having a 180° electrical length and adjusting characteristic impedances of the main line and the stub lines, it is possible to adjust a slope of a phase characteristic of a transmission line, thereby designing a feed network that reduces a frequency-phase dispersion error in a wideband.
Further, according to the present disclosure, it is possible to provide a feed network design technology that enables a planar array antenna having circular polarization to have low AR characteristics in a wideband.
According to the present disclosure, it is possible to design a feed network capable of correcting a phase dispersion error according to a change in frequency in a wideband, and thus it is expected that a planar array antenna having wideband circular polarization with excellent AR characteristics can be developed.
Exemplary embodiments of the present disclosure are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing exemplary embodiments of the present disclosure. Thus, exemplary embodiments of the present disclosure may be embodied in many alternate forms and should not be construed as limited to exemplary embodiments of the present disclosure set forth herein.
Accordingly, while the present disclosure is capable of various modifications and alternative forms, specific exemplary embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the present disclosure to the particular forms disclosed, but on the contrary, the present disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure. Like numbers refer to like elements throughout the description of the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (i.e., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).
The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Hereinafter, exemplary embodiments of the present disclosure will be described in greater detail with reference to the accompanying drawings. In order to facilitate general understanding in describing the present disclosure, the same components in the drawings are denoted with the same reference signs, and repeated description thereof will be omitted.
Referring to
Further, when viewing an antenna having a circular structure from the bottom rear, the planar array antenna R1000 may include feed networks F2000, F3100, F3200, F3300, and F3400 which are disposed in a lower area thereof, as illustrated in
The feed network F2000 disposed at the center between the quarter feed networks may be a 4-way feed network that outputs uniform power to the quarter feed networks. The 4-way feed network may be referred to as a main feed network. In view of a transmission antenna, such a main feed network may have one input port IP1 for the planar array antenna R1000 and four output ports OP2, OP3, OP4, and OP5 for the four quarter feed networks.
In order to design a planar array antenna having circular polarization with low axial ratio (AR) characteristics, it is necessary to sequentially delay the phase feeding for each quarter array (or ¼ array) by 90° clockwise or counterclockwise.
In order for a planar array antenna having circular polarization to have low AR characteristics in a wideband, amplitude and phase distribution characteristics according to a change in frequency required by the main feed network F2000 are very important. That is, in order to obtain excellent AR characteristics in a wideband, amplitude characteristics of four output signals should be the same over a desired wideband, and phase characteristics should be controlled to sequentially differ by 90°.
Referring to
The first T-branch circuit F2100 may internally include a first T-junction circuit N2100, a 180° phase offset compensation (POC) circuit network F2110 having a 180° electrical length, and a standard transmission line (STL) F2120 having a 360° electrical length, and may provide a uniform 180° phase delay difference in the wideband.
The second T-branch circuit F2200 may internally include a second T-junction circuit N2200, a 90° POC circuit network F2210 having a 180° electrical length, and a STL F2220 having a 270° electrical length, and may provide a uniform 90° phase delay difference in the wideband.
The 4-way wideband feed network described above with reference to
The first T-branch circuit F2100 and second T-branch circuits F2200 will be described in more detail with reference to
Referring to
The first POC circuit network F2110 is a 180° POC circuit network and may include one main line MTL1 and open and short stub lines STL1 attached to both ends of the main line MTL1, as illustrated in
Electrical characteristics of the first main line MTL1 include a characteristic impedance Zm1 and a first main phase θm1 (here, θm1=180°, and electrical characteristics of the first stub line include a characteristic impedance Zs1 and a first branch phase θs1 (here, θs1=45°. The characteristic impedance Zm1 of the first main line MTL1 and the characteristic impedance Zs1 of the first stub line STL1 are important design parameters for adjusting a frequency-phase dispersion slope. The characteristic impedance Zm1 of the first main line MTL1 may be referred to as a first main characteristic impedance, a phase of the first main line MTL1 may be referred to as a first main phase, the characteristic impedance Zs1 of the first stub line STL1 may be referred to as a first branch characteristic impedance, and a phase of the first stub line STL1 may be referred to as a first branch phase.
As an example, in an operation of a 40% bandwidth, optimal design parameter values of the first main characteristic impedance Zm1 and the first branch characteristic impedance Zs1 for correcting a 180° frequency-phase dispersion error are 1.62 Zo[Ω] and 1.26 Zo[Ω], respectively. Here, Zo denotes a characteristic impedance of three input and output ports and may have a value of 50Ω.
Further, an STL RTL1 having a 360° electrical length is a simple reference transmission line (RTL) and may be referred to as a first STL, and electrical characteristics of the STL RTL1 may include a first reference characteristic impedance Zo1 (here, Zo1=Zo) and a first reference phase θo1(here, θo1=360°.
Under these design conditions, when input impedances branching off to two paths is set to be identical, amplitudes of signals branching off to two paths in the operation of the 40% bandwidth may be identical to each other, and may be controlled to generate a uniform 180° phase difference.
Referring to
The second POC circuit network F2210 is a 90° POC circuit network and may include one main line MTL2 and open and short stub lines STL2 attached to both ends of the main line MTL2, as illustrated in
Electrical characteristics of the second main line MTL2 include a characteristic impedance Zm2 and a second main phase θm2(here, θm2)=180°, and electrical characteristics of the second stub line include a characteristic impedance Zs2 and a second branch phase θs2 (here, θs2=45′). The characteristic impedance Zm2 of the second main line MTL2 and the characteristic impedance Zs2 of the second stub line STL2 are important design parameters for adjusting a frequency-phase dispersion slope. The characteristic impedance Zm2 of the second main line MTL2 may be referred to as a second main characteristic impedance, a phase of the second main line MTL2 may be referred to as a second main phase, the characteristic impedance Zs2 of the second stub line STL2 may be referred to as a second branch characteristic impedance, and a phase of the second stub line STL2 may be referred to as a second branch phase.
As an example, in an operation of a 40% bandwidth, optimal design parameter values of the second main characteristic impedance Zm2 and the second branch characteristic impedance Zs2 for correcting a 90° frequency-phase dispersion error are 1.36 Zo[Ω] and 2.51 Zo[Ω], respectively. Here, Zo denotes a characteristic impedance of three input and output ports.
Further, an STL RTL2 having a 270° electrical length is a simple RTL and may be referred to as a second STL, and electrical characteristics of the STL RTL2 may include a second reference characteristic impedance Zo2 (here, Zo2=Zo) and a second reference phase θo2 (here, θo2=270°.
Under these design conditions, when input impedance branching off to two paths is set to be identical, amplitudes of the signals branching off to two paths in the operation of a 40% bandwidth are identical to each other, and may be controlled to generate a uniform 90° phase difference.
Referring to
That is,
As described above, in the feed network of the comparative example, the input return loss characteristics and the relative amplitude error between the four channels are good, but the maximum cumulative phase error between the four channels is very large, and accordingly, the frequency-phase dispersion error cannot be corrected in a wideband, and thus it is impossible to implement excellent AR characteristics in a wideband.
Table 1 summarizes and shows electrical characteristics of a 4-way uniform power distribution feed network using the difference in electrical length between the STLs of the comparative example described above.
As shown in Table 1, in the feed network of the comparative example, among characteristic parameters (S-parameters) of the channels S21, S31, S41, and S51, transmission amplitudes may have sizes of −6.0±0.2 dB and −6.0±0.6 dB, and transmission phases may have angles of 0°, −90°±18°, −180°±42°, and −270°±60° with respect to a preset reference phase.
Referring to
Table 2 summarizes and shows electrical characteristics of a 4-way feed network using the frequency-phase dispersion error correction circuit.
As shown in Table 2, in the feed network of the present embodiment, among characteristic parameter (S-parameters) of the channels S21, S31, S41, and S51, transmission amplitudes may have a uniform size of −6.0±0.3 dB, and transmission phases may have a substantially uniform difference angle of 0°, −90°±1.2°, −180°±4.3°, and −270°±5.3° with respect to a preset reference phase.
Referring to
The feed network F2000 may receive power through an input port IP1 of the first T-branch circuit F2100, and, when viewed from the front of
The above-described first power, second power, third power, and fourth power may be transmitted to at least one radiating element of each quarter array on an upper side of a planar array antenna.
Referring to
Unit radiating elements constituting the planar array antenna R1000 may be cylindrical helix elements, and in this case, a diameter of the cylindrical helix element may be about 1 wavelength and may be formed to provide axial mode radiation characteristics.
In the present embodiment, the number of entire array elements of the planar array antenna R1000, that is, the number of radiating elements is 28, and the number of radiating elements of each of quarter arrays R1100, R1200, R1300, and R1400 is 7. The quarter array composed of the seven radiating elements may be sequentially and rotatably disposed in a right direction for each quarter array. The planar array antenna R1000 may include a non-uniform 7-way power distribution feed network in order to supply beamforming power to the quarter array composed of the seven radiating elements. The non-uniform 7-way power distribution feed network may be referred to simply as a 7-way feed network.
The 7-way feed network may include one first T-branch circuit F2100, two second T-branch circuits F2200, and four power distribution circuits F3100, F3200, F3300, and F3400.
Among the four power distribution circuits, a first power distribution circuit F3100 and a second power distribution circuit F3200 may be connected to a lower side and an upper side of a second T-branch circuit F2200 positioned on one side of the first T-branch circuit F2100, respectively, and may be disposed to supply power having substantially the same amplitude and a phase difference of about 90° to two quarter arrays which are positioned in a third quadrant and a second quadrant of the planar array antenna R1000.
Further, among the four power distribution circuits, a third power distribution circuit F3300 and a fourth power distribution circuit F3400 may be connected to an upper side and a lower side of a second T-branch circuit F2200 positioned on the other side of the first T-branch circuit F2100, respectively, and may be disposed to supply power having substantially the same amplitude and a phase difference of about 90° to two quarter arrays which are positioned in a first quadrant and a fourth quadrant of the planar array antenna R1000.
Here, third power supplied to the corresponding quarter array through the third power distribution circuit F3300 may have substantially the same transmission amplitude as second power supplied to the corresponding quarter array through the second power distribution circuit F3200, and may have a phase difference of about 90°.
According to the configuration described above, when the beamforming planar array antenna R1000 of
As shown in
When a feed network for seven quarter array elements is improved to a non-uniform 7-way power distribution feed network, excellent AR characteristics of 0.5 dB or less may be obtained over a wideband.
Table 3 shows AR characteristics in a boresight direction simulated in each global positioning system (GPS) signal band for 1.176 GHz (GPS L5), 1.227 GHz (GPS L2), 1.278 GHz (GPS L6), and 1.575 GHz (GPS L1) frequencies.
The above-described beamforming planar array antenna may be formed to allow a predetermined control device to control beamforming.
Referring to
Further, the control device 5000 may further include an input interface device 5400, an output interface device 5500, a storage device 5600, and the like, optionally as necessary. The respective components included in the control device 5000 may be connected to each other through a bus 5700 to communicate with each other, or may be connected to each other through individual interfaces or individual buses with the at least one processor 5100 positioned therebetween. For example, the processor 5100 may be connected to at least one of the memory 5200, the transceiver 5300, the input interface device 5400, the output interface device 5500, and the storage device 5600 through a dedicated interface.
The processor 5100 may execute a program command stored in at least one of the memory 5200 and the storage device 5600. The processor 5100 may function to automatically adjust characteristic impedances of a main line and stub lines which are installed to correct a frequency-phase dispersion error in a wideband on the basis of at least one command or program command, thereby adjusting a slope of a phase characteristic of a transmission line. The processor 5100 may be a central processing unit (CPU), a graphics processing unit (GPU), or a dedicated processor in which the methods according to the embodiments of the present disclosure are performed.
Each of the memory 5200 and the storage device 5600 may include at least one of a volatile storage medium and a non-volatile storage medium. For example, the memory 5200 may include at least one of a read only memory (ROM) and a random-access memory (RAM).
Meanwhile, the methods of controlling the feed network for correcting the frequency-phase dispersion error in the wideband according to the present disclosure may be implemented in the form of program instructions that can be executed by various computer means, and recorded on computer readable media. The computer readable media may include program instructions, data files, data structures, etc. alone or in combination. The program instructions recorded on the computer readable media may be specially designed and configured for the present disclosure or may be known and usable to those skilled in the art of computer software.
Examples of the computer readable media include hardware devices specially configured to store and execute program instructions, such as an ROM, an RAM, a flash memory, and the like. Examples of the program instructions include high-level language code that can be executed by a computer using an interpreter or the like as well as machine language code generated by a compiler. The hardware devices described above may be configured to operate as at least one software module to perform the operations of the present disclosure, and vice versa.
Further, the above-described control device may be implemented as a hardware component, a software component, and/or a combination thereof. For example, the control device may be implemented using at least one general purpose or special purpose computer, such as a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), a programmable logic unit (PLU), a microprocessor, or another device that can execute and respond to instructions.
The control device may further include an operating system (OS) and one or more software applications running on the OS. Further, the control device may access, store, manipulate, process, and generate data in response to execution of software. It can be seen that, for convenience of understanding, there are cases in which one control device is used, but those skilled in the art will understand that the control device includes a plurality of processing elements and/or a plurality of types of processing elements. For example, the control device may include a plurality of processors or include one processor and one controller. Further, the control device may also include another processing configuration such as a parallel processor.
The operations of the method according to the exemplary embodiment of the present disclosure can be implemented as a computer readable program or code in a computer readable recording medium. The computer readable recording medium may include all kinds of recording apparatus for storing data which can be read by a computer system. Furthermore, the computer readable recording medium may store and execute programs or codes which can be distributed in computer systems connected through a network and read through computers in a distributed manner.
The computer readable recording medium may include a hardware apparatus which is specifically configured to store and execute a program command, such as a ROM, RAM or flash memory. The program command may include not only machine language codes created by a compiler, but also high-level language codes which can be executed by a computer using an interpreter.
Although some aspects of the present disclosure have been described in the context of the apparatus, the aspects may indicate the corresponding descriptions according to the method, and the blocks or apparatus may correspond to the steps of the method or the features of the steps. Similarly, the aspects described in the context of the method may be expressed as the features of the corresponding blocks or items or the corresponding apparatus. Some or all of the steps of the method may be executed by (or using) a hardware apparatus such as a microprocessor, a programmable computer or an electronic circuit. In some embodiments, one or more of the most important steps of the method may be executed by such an apparatus.
In some exemplary embodiments, a programmable logic device such as a field-programmable gate array may be used to perform some or all of functions of the methods described herein. In some exemplary embodiments, the field-programmable gate array may be operated with a microprocessor to perform one of the methods described herein. In general, the methods are preferably performed by a certain hardware device.
The description of the disclosure is merely exemplary in nature and, thus, variations that do not depart from the substance of the disclosure are intended to be within the scope of the disclosure. Such variations are not to be regarded as a departure from the spirit and scope of the disclosure. Thus, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0116379 | Sep 2022 | KR | national |
