Buck Converter and Control Method

Abstract

An apparatus includes a PWM ramp generator coupled between a switching node of a power converter and a first input of a comparator, the PWM ramp generator comprising a first resistor and a first capacitor connected in series between the switching node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node, and a PFM control circuit comprising an error amplifier and a current zero crossing detection comparator, wherein the error amplifier is coupled between a second input of the comparator and a reference node, and the PFM control circuit is configured to generate gate drive signal for the power converter when the power converter is configured to operate in a PFM mode.

Description

Claims

1. An apparatus comprising: a PWM ramp generator coupled between a switching node of a power converter and a first input of a comparator, the PWM ramp generator comprising a first resistor and a first capacitor connected in series between the switching node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node; anda PFM control circuit comprising an error amplifier and a current zero crossing detection comparator, wherein the error amplifier is coupled between a second input of the comparator and a reference node, and the PFM control circuit is configured to generate gate drive signal for the power converter when the power converter is configured to operate in a PFM mode.

2. The apparatus of claim 1, wherein the power converter comprises: a high-side switch and a low-side switch connected in series between an input voltage bus and ground, wherein a common node of the high-side switch and the low-side switch is the switching node of the power converter; andan inductor connected between the common node of the high-side switch and the low-side switch and an output of the power converter.

3. The apparatus of claim 1, further comprising: a first control switch connected between the first input of the comparator and the feedback node;a second control switch connected between the second input of the comparator and the reference node; anda third control switch coupled between the switching node and the first input of the comparator, wherein: the second control switch and the third control switch are configured to be turned on, and the first control switch is configured to be turned off when the power converter is configured to operate in a PWM mode; andthe second control switch and the third control switch are configured to be turned off, and the first control switch is configured to be turned on when the power converter is configured to operate in the PFM mode.

4. The apparatus of claim 1, further comprising: a divider comprising a third resistor and a fourth resistor connected in series between an output of the power converter and ground; anda third capacitor connected in parallel with the third resistor, wherein a common node of the third resistor and the fourth resistor is the feedback node.

5. The apparatus of claim 1, further comprising: a threshold voltage generator coupled between the second input of the comparator and an output of the error amplifier, wherein: the error amplifier is a transconductance operation amplifier;a fourth capacitor and a fifth resistor are connected in parallel between the output of the error amplifier and ground, and wherein the fourth capacitor and the fifth resistor form a pole;a non-inverting input of the error amplifier is connected to a predetermined reference;an inverting input of the error amplifier is connected to the feedback node, and wherein: a comparison of a voltage on the feedback node, and a sum of an output voltage of the error amplifier and a threshold voltage from the threshold voltage generator is used to determine an on-time of a high-side switch of the power converter; anda comparison of the voltage on the feedback node and the output voltage of the error amplifier is used to determine a turn-on instant of the high-side switch of the power converter; andthe current zero crossing detection comparator is configured to determine an on-time of a low-side switch of the power converter once a current flowing through the low-side switch of the power converter reaches zero.

6. The apparatus of claim 1, further comprising: a peak current detection comparator, wherein: the error amplifier is a transconductance operation amplifier;a fourth capacitor and a fifth resistor are connected in parallel between an output of the error amplifier and ground, and wherein the fourth capacitor and the fifth resistor form a pole;a non-inverting input of the error amplifier is connected to a predetermined reference;an inverting input of the error amplifier is connected to the feedback node, and wherein: a comparison of a current flowing through a high-side switch of the power converter and a predetermined peak current reference is used to determine an on-time of the high-side switch of the power converter; anda comparison of a voltage on the feedback node and an output voltage of the error amplifier is used to determine a turn-on instant of the high-side switch of the power converter; andthe current zero crossing detection comparator is configured to determine an on-time of a low-side switch of the power converter once a current flowing through the low-side switch of the power converter reaches zero.

7. The apparatus of claim 1, further comprising: a constant on-time generator, wherein: the error amplifier is a transconductance operation amplifier;a fourth capacitor and a fifth resistor are connected in parallel between an output of the error amplifier and ground, and wherein the fourth capacitor and the fifth resistor form a pole;a non-inverting input of the error amplifier is connected to a predetermined reference;an inverting input of the error amplifier is connected to the feedback node, and wherein: an output of the constant on-time generator is used to determine an on-time of a high-side switch of the power converter; anda comparison of a voltage on the feedback node and an output voltage of the error amplifier is used to determine a turn-on instant of the high-side switch of the power converter; andthe current zero crossing detection comparator is configured to determine an on-time of a low-side switch of the power converter once a current flowing through the low-side switch of the power converter reaches zero.

8. The apparatus of claim 7, further comprising: a resistor-capacitor filter connected to the switching node, wherein the resistor-capacitor filter is configured such that an output voltage of the resistor-capacitor filter is used to determine an output voltage of the power converter fed into the constant on-time generator when the power converter is configured to operate in the PFM mode.

9. The apparatus of claim 1, wherein: the comparator is a hysteresis comparator;the first input of the comparator is an inverting input; andthe second input of the comparator is a non-inverting input.

10. The apparatus of claim 1, wherein: a resistance value of the first resistor is at least ten times greater than a resistance value of the second resistor;the second resistor is configured to provide a leakage path for the first input of the comparator; andthe first capacitor is configured such that a majority of a DC voltage difference between an output of the power converter and the feedback node is across the first capacitor.

11. A method comprising: in a PWM mode of a power converter, configuring a plurality of control switches such that gate drive signals of the power converter are generated based on a comparison between an output of a PWM ramp generator and a predetermined reference; andin a PFM mode of the power converter, configuring the plurality of control switches such that gate drive signals of the power converter are generated based on signals generated by an error amplifier and a current zero crossing detection comparator.

12. The method of claim 11, wherein: a high-side switch and a low-side switch are connected in series between an input voltage bus and ground, wherein a common node of the high-side switch and the low-side switch is a switching node of the power converter;an inductor is connected between the common node of the high-side switch and the low-side switch and an output of the power converter;a PWM ramp generator is coupled between the switching node of the power converter and a first input of a comparator, and wherein the PWM ramp generator comprises a first resistor and a first capacitor connected in series between the switching node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node;the comparator has an output coupled to control logic and gate drive circuits;the error amplifier is coupled between a second input of the comparator and a reference node;a current zero crossing detection comparator is coupled to the control logic and gate drive circuits;a first control switch of the plurality of control switches is connected between the first input of the comparator and the feedback node;a second control switch of the plurality of control switches is connected between the second input of the comparator and the reference node; anda third control switch of the plurality of control switches is coupled between the switching node and the first input of the comparator.

13. The method of claim 12, further comprising: in the PWM mode of the power converter, configuring the second control switch and the third control switch to be turned on, and configuring the first control switch to be turned off.

14. The method of claim 12, further comprising: in the PFM mode of the power converter, configuring the second control switch and the third control switch to be turned off, and configuring the first control switch to be turned on.

15. The method of claim 12, further comprising: in the PFM mode of the power converter, comparing a voltage on the feedback node with a sum of an output voltage of the error amplifier and a threshold voltage from a threshold generator to determine an on-time of the high-side switch of the power converter;comparing the voltage on the feedback node and the output voltage of the error amplifier to determine a turn-on instant of the high-side switch of the power converter; anddetermining, by the current zero crossing detection comparator, an on-time of the low-side switch of the power converter once a current flowing through the low-side switch of the power converter reaches zero.

16. The method of claim 12, further comprising: in the PFM mode of the power converter, comparing a current flowing through the high-side switch of the power converter with a predetermined peak current reference to determine an on-time of the high-side switch of the power converter;comparing a voltage on the feedback node with an output voltage of the error amplifier to determine a turn-on instant of the high-side switch of the power converter; anddetermining, by the current zero crossing detection comparator, an on-time of the low-side switch of the power converter once a current flowing through the low-side switch of the power converter reaches zero.

17. The method of claim 12, further comprising: in the PFM mode of the power converter, determining an on-time of the high-side switch of the power converter based on an output of a constant on-time generator;comparing a voltage on the feedback node with an output voltage of the error amplifier to determine a turn-on instant of the high-side switch of the power converter; anddetermining, by the current zero crossing detection comparator, an on-time of the low-side switch of the power converter once a current flowing through the low-side switch of the power converter reaches zero.

18. A system comprising: a high-side switch and a low-side switch connected in series between an input voltage bus and ground, wherein a common node of the high-side switch and the low-side switch is a switching node;an inductor connected between the common node of the high-side switch and the low-side switch and an output of the system;a PWM ramp generator coupled between the switching node and a first input of a comparator, the PWM ramp generator comprising a first resistor and a first capacitor connected in series between the switching node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node; anda PFM control circuit comprising an error amplifier and a current zero crossing detection comparator, wherein the error amplifier is coupled between a second input of the comparator and a reference node, and the PFM control circuit is configured to generate gate drive signal for the system when the system is configured to operate in a PFM mode.

19. The system of claim 18, further comprising: a first control switch connected between the first input of the comparator and the feedback node;a second control switch connected between the second input of the comparator and the reference node; anda third control switch coupled between the switching node and the first input of the comparator, wherein: the second control switch and the third control switch are configured to be turned on, and the first control switch is configured to be turned off when the system is configured to operate in a PWM mode; andthe second control switch and the third control switch are configured to be turned off, and the first control switch is configured to be turned on when the system is configured to operate in the PFM mode.

20. The system of claim 18, further comprising: a divider comprising a third resistor and a fourth resistor connected in series between an output of the system and ground;a third capacitor connected in parallel with the third resistor, wherein a common node of the third resistor and the fourth resistor is the feedback node; anda resistor-capacitor filter connected to the switching node, wherein the resistor-capacitor filter is configured such that an output voltage of the resistor-capacitor filter is used to determine an output voltage of the system when the system is configured to operate in the PFM mode.