Patent Application
20050231181
This Utility Patent Application claims priority to German Patent Application No. EP 04 008 878.3 filed on Apr. 14, 2004, which is incorporated herein by reference.
The present invention provides a buck converter, and in particular, a buck converter with low loss current measurement.
Buck converters are switching converters used to convert an input voltage into an output voltage that is lower than the input voltage. The basic design of such buck converters is described on page 176 of Stengl, J. P.; Tihanyi, J.: “Leistungs-MOS-FET-Praxis” (Practical Application of MOS-FETs), 2nd edition, Pflaum Verlag, Munich, for example. The key element of a buck converter is an inductive storage element that is driven in accordance with a pulse width-modulated drive signal, and connected during activation periods to a supply potential and during deactivation periods to a reference potential.
To regulate the output voltage to maintain an approximately constant value independent of the input current of a load connected to output terminals, a control system for measuring the output voltage or changes in the output voltage is provided in switching converters of this kind. If the output voltage deviates from a specified reference value, the power input of the buck converter is changed by altering the activation period to set the output voltage to the reference value again. In the case of buck converters working with so-called current mode control, the time behavior of the current through the inductor is used for generating the pulse width-modulated drive signal. The time behavior, which corresponds approximately to a delta signal characteristic, is compared with a control signal dependent on the output voltage in order to define the beginning or end of an activation period. The beginning or end of the activation period is defined with a fixed clocking pattern.
A buck converter with current mode control is described on pages 492-495 of Tarter, R. E.: “Solid-State Power Conversion Handbook”, Wiley & Sons, New York, 1993, ISBN 0-471-57243-8, for example.
The measurement of the current through the inductor is often the cause of problems in current mode buck converters.
A buck converter for alternate connection of the inductor to the supply and reference potentials is described in U.S. Pat. No. 6,166,528. The converter has a half-bridge circuit with two transistors: the first transistor is connected between the inductor and the supply potential, while the second transistor is connected between the inductor and the reference potential. A current measuring system measures the current flowing through the second transistor in order to provide a current measuring signal. The first transistor is switched on any time the current through the second transistor falls below the value of a control signal that varies with the output voltage, and switched off periodically according to a clock signal. This buck converter is operated in the so-called valley current mode because the times at which the current through the inductor reaches a local minimum value are the principal factors for switching on the first transistor or for the beginning of an activation period.
Embodiments of the invention provide a buck converter with low loss current measurement. In one embodiment, the invention provides a buck converter including at least one inductive storage element and a signal generation circuit configured to produce a load current signal. The signal generation circuit includes a ramp signal generation circuit configured to generate a ramp signal, a DC signal generation circuit connected to the inductive storage element that generates a DC signal that varies with a direct component of the load current, and a logic circuit, to which the ramp signal and the DC signal are fed, for producing the load current signal.
The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
The present invention provides a buck converter with a current measuring system to measure the current through the inductor.
In one embodiment, the buck converter for converting an input voltage into an output voltage available at an output includes at least one inductive storage element with one connection connected to the output terminal and a second connection connected during activation periods to a supply potential and during deactivation periods to a reference potential in accordance with a drive signal. The buck converter also includes a drive circuit for providing the drive signal and a signal generation circuit for producing a load current signal. A control signal that varies with the output voltage and a load current signal dependent on the current through the inductive storage element are fed to the drive circuit in the buck converter. The signal generation circuit contains a ramp signal generation circuit for providing a ramp signal with a ramp that varies with the input and output voltages, as well as a DC signal generation circuit that is connected to the inductive storage element for producing a DC signal that varies with the direct component of a load current through the coil, and a logic circuit, to which the ramp signal and the DC signal are fed, for producing the load current signal.
Current through the inductor of a buck converter is approximately proportional to the input and output voltages, and in particular, proportional to the difference between the input voltage and the lower output voltage. The ramp signal generation circuit uses this relationship to generate a ramp signal without having to measure the current through the inductor. For buck converters operating in delta current mode—i.e., in which the inductance does not fully decline in commutation before beginning a new activation period, the current through the inductor exhibits a direct component that cannot be immediately determined using the input and output voltages. The DC signal generation circuit produces a signal that reproduces the direct component of the current through the inductor in order to provide a load current signal at the output of the logic circuit that is at least approximately proportional to the load current through the inductor.
The ramp signal generation circuit in one embodiment has a voltage-controlled current source that produces a current that varies according to the difference between the input voltage and the output voltage, and a capacitive storage element that is connected to the current source and which provides the ramp signal.
The DC signal generation circuit in one embodiment has a sample-and-hold element connected to the second connection of the inductive storage element. The sample-and-hold element samples the potential applied to the second connection in synchronization with the clock of the drive signal in order to provide the DC signal. The sample-and-hold element is designed, for example, to sample the potential at the beginning of an activation period.
To measure the potential at the second connection of the inductive storage element, the sample-and-hold element in one embodiment measures the voltage over a freerunning element of the buck converter that is connected between the second connection and the reference potential.
In a different embodiment, the DC signal generation circuit has a low-pass filter, which is connected in parallel to the inductive storage element and at which the DC signal is provided. A sample-and-hold element can be optionally connected after the low-pass filter to provide the DC signal.
The inductive storage element L absorbs energy from the input voltage Vcc when the first transistor T1 is conducting, and conveys the energy to a load Z connected to the buck converter via the output terminal K3 when the first transistor T1 is disabled. A capacitor Cout connected between the output terminals K3, K4 smooths the output voltage Vout. The second transistor T2 works as a freerunning element for the load current IL flowing through the inductor L when the first transistor T1 is blocked. The first transistor T1, through which the power input of the buck converter, and therefore the output voltage Vout, are controlled, is crucial to the operation of the buck converter. The second transistor T2 can also be replaced by a free-wheeling diode in the well-known manner. A drive circuit 10 is provided to drive the first transistor T1 with a particular drive signal S1, and in this case to also drive the second transistor T2 with a complementary drive signal S2 to the first drive signal S1. This drive circuit 10 produces pulse width-modulated drive signals S1, S2 in relation to a control signal Sea and a load current signal S26 in order to drive the two transistors T1, T2.
The illustrated drive circuit 10 is designed to close the first switch T1 synchronously with a clock signal CLK and to keep the switch closed for an activation period Ton which varies with the control signal Sea and the load current signal S26. The resulting load current IL obtained by driving the first switch T1 is illustrated in
The control signal Sea is generated by a control system 30, to which the output voltage Vout, on the one hand, and a reference voltage Vref on the other, are fed. The reference voltage Vref specifies a reference value for the output voltage Vout. The control system can be constructed, for example, as a proportional controller (P-controller), an integral controller (I-controller) or proporional-plus-integral controller (PI-controller). It provides the control signal Sea in relation to the difference between the output voltage Vout and the reference voltage Vref; in the case of a P-controller only the current difference between the output voltage Vout and the reference voltage Vref is considered in the control signal Sea, while for I-controllers and PI-controllers, the earlier behavior of the output voltage Vout is considered in the control signal Sea.
The load current signal S26 is produced by a signal generation circuit that includes a ramp signal generation circuit 20 and a DC signal generation circuit 40.
The ramp signal generation circuit produces a ramp signal Sr, which exhibits a rising edge during the activation periods of the first transistor T1 whose slope is proportional to the difference between the input voltage Vcc and output voltage Vout. The ramp signal generation circuit 20 has an amplifier 24, to which the input voltage Vcc and the output voltage Vout are fed, and which produces an output current 124 that is proportional to the difference between the input voltage Vcc and the output voltage Vout. The following relationship applies:
I24=Gm1·(Vcc−Vout) (1)
The amplifier 24 has the function of a voltage-controlled current source.
A capacitor 28 is connected between an output of the amplifier 24 and the reference potential GND. This capacitor 28 is charged by the output current of the amplifier 24 during the activation periods Ton of the first transistor T1. The voltage V28 at the capacitor 28 during the activation period Ton is defined by the following:
V28=(I24·t)/C=(Gm1·(Vcc−Vout)·t)/C (2)
where
C is the capacitance of the capacitor 28 and t the time that has elapsed since the beginning of the corresponding activation period of the first transistor T1. The voltage V28 at the capacitor 28 is measured by an optional second amplifier 23, at whose output the ramp signal Sr is provided. The ramp signal Sr is defined as follows:
Sr=Gm2·V28=Gm2·Gm1/C·(Vcc−Vout)·t (3)
The voltage V28 at the capacitor 28—and therefore the ramp signal Sr—starts to rise at the beginning of an activation period from the reference potential GND each time. To achieve this, the capacitor 28 is short-circuited each time after opening the first transistor T1 by a switch 27 connected in parallel to the capacitor 28. The switch 27 is driven complementary to the first transistor T1, and is open when the first transistor T1 is conducting and closed when the first transistor T1 is disabled. A control signal S12 that has yet to be explained is provided in the drive circuit 10. This control signal S12 is converted by means of a driver circuit I1 to the first and second drive signals S1, S2 of the first and second transistors T1, T2. The time behavior of the first drive signal S1 matches the time behavior of the control signal S12; the sole purpose of the driver circuit 11 is to adjust the control signal S12 to a level suitable for driving the first transistor T1. The control signal S12 is also used with an inverter 25 to drive the switch 27 connected in parallel to the capacitor 28 in order to open the switch 27 when the first transistor T1 is conducting, and to close the switch 27 when the first transistor T1 is disabled.
e and 4h illustrate the time behavior of the ramp signal Sr and control signal S12 along with that of the first drive signal S1. As explained, the ramp signal Sr exhibits rising edges during activation periods Ton of the first transistor T1. Remembering equation 4, the slope of the rising edge is proportional to the difference between the input voltage Vcc and the output voltage Vout.
The following equation defines the load current IL through the inductor L when the first transistor T1 is conducting:
IL=(Vcc−Vout)·t/L+I0 (4)
As can be seen in
To provide a DC signal SO proportional to the direct component 10 of the load current IL, the buck converter has a DC signal generation circuit 40, which in the example contains a sample-and-hold element 41 and an optional amplifier 42 connected after the sample-and-hold element 41. The input of the sample-and-hold element 41 is connected to the second connection of the inductor L to sample the voltage V2 between the second connection and the reference potential GND when the first transistor T1 is disabled and the second transistor T2 is conducting. The voltage V2 is defined as follows when the second transistor T2 is conducting:
V2=IL−Rdson2 (5),
where
Rdson2 is the on-resistance of the second transistor T2. The clock signal CLK that defines the beginning of the activation periods is fed to the sample-and-hold element 41. The sample-and-hold element 41 is designed to sample the load current value IL over the voltage V2 directly or each time the first transistor T1 is activated or shortly before that time. This is equivalent to saying that the sample-and-hold element 41 samples the minimum value of the load current IL.
The sample-and-hold element 41 holds the sampled value for the activation period of the first transistor T1. To clear the sampled value upon expiry of the activation period, the control signal S12 is fed to a reset input of the sample-and-hold element 41, for which the sample-and-hold element 41 is reset with the falling edge of the control signal S12.
An output signal of the sample-and-hold element 41 corresponding to the held sampled value is amplified by the optional amplifier 42 to produce the DC signal S0. What is crucial here is that the DC signal S0 exhibits at least an approximately constant amplitude matching the sampled value during the activation period of the first transistor T1.
The DC signal S0 is proportional to the sampled local minimum values of the load current IL and is therefore proportional to the direct component 10 as shown in
The ramp signal Sr and the DC signal S0 are fed to a logic circuit 26, which is designed in the embodiment example as a signal adder and which provides a load current signal S26 corresponding to the sum of the DC signal S0 and the ramp-shaped signal Sr. For the load current signal S23 to be proportional to the load current IL, the proportionality factor between the DC signal S0 and the direct component 10 must match the proportionality factor between the ramp signal Sr and the ramp-shaped signal component of the load current IL. To ensure this relationship, the following equation must apply:
Rdson2·Gms=Gm1·G-2·L/C (6)
The drive circuit 10 that produces the first drive signal S1 from the load current signal S26 and the control signal Sea has, in the embodiment example, an RS flip-flop 12, to whose setting input the clock signal CLK is fed, and at whose non-inverted output the control signal S12 is available, which is converted by means of the driver circuit I1 to the first drive signal S1. A level shifter 15 can be optionally connected before the setting input of the flip-flop 12. In this case, the clock signal CLK is fed to the level shifter 15, which adjusts the clock signal to a level suitable for setting the flip-flop 12. The clock signal CLK can be generated in the drive circuit 10, which is not treated further here, or fed in from an external clock generator.
As already explained, the clock signal CLK defines the activation times for the first transistor T1. The transistor T1 remains driven in a conducting state until the flip-flop 12 is reset and the control signal S12, and therefore the first drive signal S1, change to a low level. The flip-flop 12 is reset in accordance with the load current signal S26 and the control signal Sea: it is reset each time the load current signal S26 rises during the activation period to the value of the control signal Sea.
f illustrates the time behavior of the control signal Sea when using a proportional controller 30, in addition to the time behavior of the load current signal S26. Note that
A subtractor 14, whose output is connected to a comparator 13, is included in the drive circuit 10—as shown in
The following principle always applies to the control of the buck converter shown in
The issue is how fast the transient response should be. Of course, the longer the RC-time-constant is, the slower is the system. Since the current in the inductor is sampled at the end of the switch-off time, the current ripple (AC component) can be neglected. So, it is not necessary to have a perfect matching of the two-time constant RC and L/RL. This means that if RC is close enough to L/RL the response is good anyway, no matter what the AC component is.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 04 008 878.3 | Apr 2004 | EP | regional |
