Patent Application
20240195304
This application claims priority to European Patent Application No. 22212913.2, filed on Dec. 12, 2022. The afore-mentioned patent application is hereby incorporated by reference in its entirety.
The present disclosure concerns a buck/boost conversion device and a control circuit for a bidirectional buck/boost converter.
Bidirectional buck/boost converters and their control circuits are commonly known, from for example U.S. Pat. No. 8,593,115 B2.
In common control circuits for buck/boost converters, especially for battery chargers, expensive and complicated PWM (pulse width modulation) controllers are often employed, which commonly comprise a high number of inputs and outputs for controlling switches of the buck/boost converter, especially in full-bridge applications, in which the circuit is more complex and less cost-effective.
It is an object of the present disclosure to provide a simple and cost-effective control circuit for a bidirectional buck/boost converter as well as a buck/boost conversion device with these advantages.
The solution of this object is achieved by the features of the independent claim. The dependent claims concern advantageous embodiments of the present disclosure.
In particular, the solution of this disclosure is achieved by a control circuit for a bidirectional buck/boost converter. The control circuit comprises a buck/boost detection unit configured to detect and output a mode of operation of the bidirectional buck/boost converter selected from buck mode and boost mode. Further, the control circuit comprises a voltage/current regulator unit configured to receive the mode of operation output from the buck/boost detection unit and configured to output a corresponding regulating signal based on the mode of operation. Furthermore, the control circuit comprises a PWM (Pulse Width Modulation) control unit configured to receive the regulating signal from the voltage/current regulator unit and configured to output a PWM control signal based on the regulating signal. The control circuit comprises a gate drive signal toggle unit configured to receive the PWM control signal and the mode of operation and configured to generate and output gate drive signals for driving switching operations of a plurality of switches of the buck/boost converter based on the mode of operation and on the PWM control signal.
Preferably, in the foregoing and in the following, the term “mode of operation” refers to “buck” or “boost” mode. Further, the mode of operation may preferably be “off”, in which the converter is switched off entirely, or disconnected, for instance for protection measures. Since the modes of operation, namely buck and boost, are highly similar in a bidirectional buck/boost converter, and are commonly known, the following will generalize the control thereof to “based on mode of operation”.
In the foregoing and in the following, “inputs” and “outputs” are described. Preferably, such “inputs” and “outputs” refer to signal inputs and outputs. More preferably, when referring to components having for example “exactly one” or “exactly two” inputs or outputs, this refers to inputs and outputs of (control) signals. Preferably, however, the components may comprise for instance a connection to ground and/or a reference voltage and/or a supply voltage and/or a clock signal. For instance, if a component is explained as comprising “exactly one input”, this means that said component comprises exactly one signal input, but may further comprise a connection (or input) for a supply voltage and a connection to ground. In other words, “inputs” and “outputs” as set forth herein refer to a signal logic of the control circuit and/or the buck/boost converter.
Preferably, in the foregoing and in the following, when referring to control signals, “high” and “ON” on the one hand and “low” and “OFF” on the other may be used interchangeably/synonymously.
Preferably, in the foregoing and in the following, regulating signals for the buck or boost mode are discussed. The general selection of driving the buck/boost converter either in buck mode or boost mode is determined based on a command signal. This command signal is preferably an external signal, which is input to the control circuit according to the present embodiments and examples, for example by a system controller.
In addition or alternatively thereto, preferably, the command signal is determined based on detection of characteristic values within the control circuit and/or within the buck/boost converter, i.e. determined/generated internally within the control circuit.
Preferably, the buck/boost detection unit is configured to receive the command signal. Based on the command signal, the buck/boost detection unit outputs a signal indicating buck or boost mode, also referred to as “buck active signal” and “boost active signal”. For example, the buck/boost detection unit preferably outputs a high signal as buck active signal and a low signal as boost active signal, or vice versa.
Preferably, the buck/boost detection unit is configured to generate the command signal, i.e. determine whether to operate the buck/boost converter in buck mode or boost mode. Preferably, the buck/boost detection unit is configured to receive voltage values from sensing units at an input side and at an output side, respectively, of the buck/boost converter. For example, such sensing units are in the following referred to as “first voltage sensing unit” and “second voltage sensing unit”. Further, the buck/boost detection unit is preferably configured to compare these input and output side voltage values and determine whether to operate in buck mode or boost mode based thereon, i.e. determine the command signal based thereon. The buck/boost detection unit then outputs a high signal as buck active signal and a low signal as boost active signal, or vice versa.
Preferably, due to the control circuit comprising the gate drive signal toggle unit which generates and outputs the gate drive signals for driving switching operations, these functions are not necessarily carried out by the PWM control unit. In other words, preferably, the PWM control unit does not generate and directly output gate drive signals to the switches of the buck/boost converter. Preferably, the PWM control unit does not directly output any signals to the switches of the buck/boost converter. Thereby, the PWM control unit is simplified and the control circuit can thus be realized in a cost-effective manner.
In an embodiment, the PWM control unit is a single-ended PWM controller which provides only one output signal. In other words, preferably, the PWM control unit comprises only a single signal output for outputting a signal driving or controlling switches and/or operations of the buck/boost converter.
In another embodiment, the PWM control unit comprises one or more further outputs, especially output pins, which are, however, not (directly) used to drive switches and/or control the buck/boost converter. For instance, the PWM control unit may comprise one or more reference outputs outputting a reference voltage, for instance a 5 V reference voltage.
Preferably, the buck/boost detection unit and/or the voltage/current regulator unit and/or the PWM control unit and/or the gate drive signal toggle unit are separate components, especially separate integrated circuits (henceforth “ICs” or “IC”). Preferably, the PWM control unit and the gate drive signal toggle unit are separate components and are especially not components of a single IC.
Preferably, the gate drive signal toggle unit has two inputs, namely the PWM control signal output by the PWM control unit and the mode of operation output from the buck/boost detection unit. Preferably, the gate drive signal toggle unit has exactly two inputs, especially exactly and only the foregoing described inputs.
Preferably, the gate drive signal toggle unit has two outputs. Preferably the gate drive signal toggle unit has exactly two outputs.
In one advantageous embodiment, the gate drive signal toggle unit is configured to output one drive signal for a first switch and one drive signal for a second switch. Therein, based on the mode of operation, the gate drive signal toggle unit is configured to generate a first drive signal by inverting the PWM control signal an odd number of times. For example, the PWM control signal is inverted once or three times or five times, etc. Therein, the inverted drive signal is especially a synchronous rectification signal.
Preferably, the number of inversions for the odd PWM control signal is one. In other words, the gate drive signal toggle unit is configured to output the first drive signal as an inverted PWM control signal, in which the PWM control signal received from the PWM control unit is inverted.
Preferably, the inverted PWM control signal is output to at least one switch, preferably exactly one switch, of the buck/boost converter.
Preferably, in the foregoing and in the following, the term “one switch” also encompasses an exemplary possibility in which one or each of the aforementioned switches (first switch and/or second switch) is respectively replaced by a plurality of switches connected in parallel as a switch unit, for example for current distribution. Therein, each of such switch units is preferably driven in common by a same PWM control signal. In other words, preferably, the once-inverted PWM control signal is output to one switch unit, and the twice-inverted PWM control signal is output to another switch unit of the buck/boost converter.
Preferably, the gate drive signal toggle unit is further configured to generate a second drive signal by inverting the PWM control signal an even number times. In other words, preferably, the second gate drive signal corresponds to an even number of inversions of the PWM control signal.
Preferably, the even number of inversions for the PWM control signal may also be zero, zero being an even number. In such a case, the “even inverted PWM control signal” corresponds to the PWM control signal output by the PWM control unit. Further preferably therein, the “odd inverted PWM control signal” corresponds to a single inversion. Thus, in such a preferable case, the PWM control signal is input into one switch (or switch unit), and the once-inverted PWM control signal is input into another switch (or switch unit) as a synchronous rectification signal.
Preferably, the first drive signal and the second drive signal are therefore inverted with respect to one another. Thereby, the second drive signal is used as a drive signal for the second switch of the buck/boost converter essentially controlling the bucked or boosted voltage, whereas the first drive signal (the inverted signal) is used for synchronous rectification of the first switch. Essentially, the first switch thereby replaces a diode operation in the buck/boost converter. Thereby, preferably, the second switch is “ON” when the first switch is “OFF” and vice versa.
Preferably, the gate drive signal toggle unit comprises at least one inverter. In the exemplary case of the even inversion being an inversion of zero, the signal is not input/output into/from an inverter. In this case, the gate drive signal toggle unit preferably comprises only one inverter for inverting the odd inverted PWM control signal once. Further preferably, the gate drive signal toggle unit comprises two inverters. Therein, preferably, the even PWM control signal is inverted twice by being input/output to both inverters, or is inverted zero times by not being input/output to any one of the two inverters, and the odd PWM control signal is inverted once by being input/output to only one inverter.
Preferably, the at least one inverter is a Schmitt trigger, more preferably an inverting Schmitt trigger. Preferably, the PWM control signal is input to a first inverter of the gate drive signal toggle unit, especially as an input of the gate drive signal toggle unit. The first inverter preferably outputs the inverted PWM control signal to another inverter and, preferably in parallel, towards an output and/or further components of the gate drive signal toggle unit. The second inverter preferably receives the inverted PWM control signal and outputs towards an output and/or further components of the gate drive signal toggle unit.
Preferably, the gate drive signal toggle unit comprises an on-time-duration limitation unit. The on-time duration limitation unit is configured to limit a time-duration of at least one of the gate drive signals to a maximum threshold value. Therein, the on-time-duration limitation unit is configured to set said gate drive signal(s) to low when the on-time-duration of the gate drive signal reaches the maximum threshold value. Thereby, preferably, a scenario is avoided in which the PWM control unit is turned off, thereby constantly outputting low, and the gate drive signal toggle unit thus constantly outputting high (via the odd inversion), which can otherwise damage the control circuit and/or the buck/boost converter and/or switches thereof.
Preferably, the maximum threshold value is a time value. Preferably, the maximum threshold value is roughly equal to (or rather an inversion of) a switching frequency of the buck/boost converter. For example, the maximum threshold value is set to roughly 10 us at an exemplary switching frequency of 100 KHz.
In one advantageous embodiment, the gate drive signal toggle unit comprises a dead-time generation unit configured to generate a dead-time between the gate drive signals. Thereby, a possible short-circuit is prevented by preventing “ON” overlap between the gate drive signals for the first and the second switches. Preferably, the dead-time is for example roughly 200 ns.
Preferably, at least one of the switches and/or at least one of the switch units comprises a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Preferably, the at least one MOSFET is an SiC—, GaN—, or Si-MOSFET. In addition or alternatively thereto, one or more switches is preferably an IGBT (Insulate-Gate Bipolar Transistor), or the like.
In a preferable embodiment, the PWM control signal is input to the first inverter. The first inverter inverts the PWM control signal and outputs the once-inverted PWM control signal to the second inverter and additionally to the on-time-duration limitation unit. The on-time-duration limitation unit preferably outputs the (duration limited) once-inverted PWM control signal to a buck/boost mode selection logic. The second inverter preferably outputs the (even inverted) PWM control signal also to the buck/boost mode selection logic unit. The buck/boost mode selection logic unit is preferably connected to or comprises the input for the mode of operation signal output by the buck/boost detection unit. The buck/boost mode selection logic unit selects, based on the mode of operation, which PWM control signal (odd inverted or even inverted) is to be output to which output of the gate drive signal toggle unit. In other words, the buck/boost mode selection logic unit selects which switch of the buck/boost converter is to receive which PWM control signal. Preferably, the buck/boost mode selection logic unit outputs the two PWM control signals to the dead-time generation unit, which generates the dead-time between the two PWM control signals before outputting these to the respective switches.
Preferably, during buck mode for instance, the PWM control signal inverted an odd number of times and duration limited (i.e. the synchronous rectification signal) is the signal output to the second switch of the buck/boost converter. Preferably, the PWM control signal inverted an even number of times is output to the first switch of the buck/boost converter. During boost mode, the opposite is preferably the case.
Preferably, the control circuit comprises a high-side/low-side driver unit configured to receive the gate drive signals output from the gate drive signal toggle unit and configured to amplify the gate drive signals and output the amplified gate drive signals to the switches. Preferably, the gate drive signal toggle unit outputs a relatively low voltage signal, for example 5 V at roughly 10 mA. The PWM control signal output by the PWM control unit is preferably roughly 12 V to 15 V. Therefore, preferably, the gate drive signals output by the gate drive signal toggle unit are amplified, preferably to a current of roughly one to multiple amp (A), so as to quickly drive the switches.
Preferably, the high-side/low-side driver unit comprises two inputs for the even and odd inverted PWM control signals output by the gate drive signal toggle unit and further comprises two outputs for the amplified PWM control signals. Preferably, the high-side/low-side driver unit comprises exactly these two inputs and exactly these two outputs.
Preferably, the high-side/low-side driver unit receives the two inputs directly from the gate drive signal toggle unit (preferably the dead-time generation unit) and preferably outputs the amplified PWM control signals directly to the switches.
Preferably, the synchronous rectified switch is deactivated at low output current so as to prevent back-sourcing to the input voltage.
Preferably, the high-side/low-side driver unit comprises at least one charge-pump for generating the supply voltage of the high-side/low-side driver unit.
Further preferably, the at least one charge-pump for supplying the first switch is implemented in the high-side/low-side driver unit so as to start and source the high-side/low-side driver unit with a connected output of the converter, for example, a connected battery and in particular if the second switch is deactivated e.g. at low currents to prevent back-sourcing. In such cases, when said second switch is deactivated, mere common bootstrap supplies may not work at pre-biased outputs (i.e. in the exemplary case of a battery connected to output). The at least one charge pump thus provides a source voltage for the high-side/low-side driver unit above ground voltage.
In one advantageous embodiment, the control circuit comprises a plurality of current sensing units, in which each of the plurality of current sensing units senses current of one of the plurality of switches. Preferably, each current sensing unit is connected in series with one switch. The control circuit preferably comprises a current sense toggle unit configured to receive a current value output by each of the current sensing units, configured to receive the mode of operation, and configured to output the current value sensed by one of the current sensing units based on the mode of operation to the PWM control unit. In other words, preferably, the current sense toggle unit toggles, based on the mode of operation, the current values sensed by which one of the current sensing units is to be output to the PWM control unit, i.e. toggles the current value of which switch to be output to the PWM control unit. The PWM control unit uses the input current value for generating and regulating the PWM control signal.
In one advantageous embodiment, the control circuit comprises a buck/boost DC sensing unit configured to sense a current output by the buck/boost converter and is configured to feed the sensed current back to the voltage/current regulator unit.
Preferably, the buck/boost DC sensing unit comprises a resistor, especially a shunt resistor, for measuring the current. The direction of current flowing through the resistor of the buck/boost DC sensing unit during buck operation is opposite the direction of current flowing through said resistor during boost operation.
In the preferable case of the resistor being a shunt resistor, this provides a limitation of the maximum battery current and further an output power limitation in boost mode. Further, the shunt resistor provides advantageously more precise charging current regulation in buck mode.
Preferably, multiple buck/boost converters and control circuits are connected in common on an input side, for example in common to an input bus, and are each connected to a battery or battery pack. In such an exemplary case, the shunt resistor preferably provides current balancing between such multiple buck/boost converters between the multiple batteries or battery packs, especially in boost mode (i.e. especially when discharging the multiple batteries or battery packs).
Preferably, the buck/boost DC sensing unit comprises two outputs. A first output is preferably configured to output a current value during buck mode (henceforth “buck out signal” or “buck out current signal”). A second output is preferably configured to output a current value during boost mode (henceforth “boost out signal” or “boost out current signal”). Therein, the buck/boost DC sensing unit is preferably configured such that the first output only outputs a current value during buck mode, and such that the second output only outputs a current value during boost mode.
Preferably, the voltage/current regulator unit is configured to regulate the voltage and/or current regulating signal based on the fed back sensed current. Preferably, the voltage/current regulator unit is configured to regulate the voltage and/or current regulating signal based on the aforementioned buck out or boost out signals.
Advantageously, the voltage/current regulator unit comprises a buck regulator subunit and a boost regulator subunit. Each buck/boost subunit preferably comprises an input for receiving the respective buck out or boost out signal from the respective output of the buck/boost DC sensing unit. Preferably, the buck regulator subunit is de-activated by a non-zero boost out signal, and the boost regulator subunit is de-activated by a non-zero buck out signal.
Further preferably, the buck regulator subunit and the boost regulator subunit are connected in parallel, such that the voltage/current regulator unit outputs a regulating signal irrespective of the mode of operation.
Advantageously, the control circuit further comprises a first voltage sensing unit, which is configured to sense a voltage at the input side of the converter. Further advantageously, the control circuit further comprises a second voltage sensing unit, which is configured to sense a voltage at the output side of the converter. Preferably, the first and second voltage sensing units do not correspond to the buck/boost detection unit or to the buck/boost DC sensing unit.
Preferably, the buck regulator subunit is configured to receive a voltage value sensed by the second voltage sensing unit of the output side of the converter. Further preferably, the boost regulator subunit is configured to receive a voltage value sensed by the first voltage sensing unit of the input side of the converter.
Further advantageously, each of the buck regulator subunit and the boost regulator subunit are configured to output a regulated current and a regulated voltage.
Further preferably, each subunit is configured to output the regulated current based on a comparison of an external reference signal with the respective buck out or boost out current signal. Preferably, the external reference signal is input to the control circuit from, for instance, the system controller. For instance, the reference signal indicates a target current value for the buck/boost converter. For instance, the reference signal is preferably a fixed internal value.
Further preferably, each subunit is configured to output the regulated voltage based on a comparison of the external reference signal (indicating, for instance, a target voltage value) with the voltage value sensed by the first voltage sensing unit or the second voltage sensing unit.
Preferably, the boost regulator subunit is configured to receive the buck active signal, and the buck regulator subunit is configured to receive the boost active signal. In both cases, the respective subunit is configured to be de-activated when the (opposite) respective active signal is non-zero.
Further preferably, the voltage regulation of the boost regulator subunit has a falling characteristic at rising load, i.e. the higher the output current, the lower the regulated booster output voltage. Due to the falling output voltage characteristic, an output current balance is preferably achieved if two or more modules are used in parallel.
In summary, the voltage/current regulator unit preferably comprises an input for buck out current signal and an input for reference current (buck regulator subunit current regulation), an input for voltage value at the output side (from second voltage sensing unit) and an input for reference voltage (buck regulator subunit voltage regulation), an input for boost out current signal and an input for reference current (boost regulator subunit current regulation), an input for voltage value at the input side (from first voltage sensing unit) and an input for reference voltage (boost regulator subunit voltage regulation). Further, the voltage/current regulator unit preferably comprises an input for boost active signal for de-activating buck regulator subunit voltage regulation and an input for buck active signal for de-activating boost regulator subunit voltage regulation.
Preferably, the PWM control unit comprises a comparator configured to compare the regulated signal from the voltage/current regulator unit with the signal from the current sense toggle unit, i.e. with the signal from one of the current sensing units. The PWM control unit preferably outputs the PWM control signal based on the output of the comparator. Thereby, preferably, the PWM control unit is configured to perform peak current mode modulation based on said regulated signal.
Preferably, the PWM control unit comprises a first pin, commonly referred to as “output/compensation” pin. Commonly, the compensation pin is connected to an internal error amp (op amp) used for instance as a voltage regulator. Preferably, in the present control circuit, the internal error amp is used solely as a voltage follower, since the external voltage/current regulator unit of the control circuit regulates for buck and boost mode.
Preferably, the PWM control unit comprises a second pin, commonly referred to as “voltage feedback input”, which is connected to a negative input of the error amp. Preferably, the signal output from the voltage/current regulator unit is input to this pin.
Preferably, the PWM control unit comprises a third pin, commonly referred to as “current sense” pin. Preferably, the signal output from the current sense toggle unit (the sensed current of the respective switch) is input to this pin as a positive input of the PWM control unit comparator.
Preferably, the signal output from the current sense toggle unit input to the third pin additionally comprises a slope compensation signal.
Preferably, the PWM control unit comprises a fourth pin, commonly referred to as “RT/CT” pin, which is connected to a grounded capacity (“CT”) and a resistor (“RT”) for defining the switching frequency and the maximum on duration of the PWM control signal. In one embodiment of the present disclosure, the switching frequency is roughly 100 kHz and the maximum on duration is roughly 97%.
Preferably, the PWM control unit comprises a fifth pin, commonly referred to as ground pin, with which the PWM control unit is grounded.
Preferably, the PWM control unit comprises a sixth pin, commonly referred to as output pin, via which the PWM control unit outputs the PWM control signal.
Preferably, the PWM control unit comprises a seventh pin, commonly referred to as “VCC” pin or “power supply pin”, via which the PWM control unit receives supply voltage.
Preferably, the PWM control unit comprises an eighth pin, commonly referred to as “VREF” pin, which is the reference voltage output by the PWM control unit, which is preferably 5 V.
Preferably, the PWM control unit comprises only the aforementioned eight pins.
In one advantageous embodiment, the buck/boost converter comprises a bus connection, for example for connection with mains and/or an external power supply, as an input. Further preferably, the buck/boost converter comprises an output side connection, for example for connection with a battery pack.
For ease of explanation, in the following, “input” will be referred to as the input side during buck mode. It however goes without saying that during boost mode, “input” may be the “output” of the buck mode, and vice versa. In such an exemplary case, when the mains is a 24 V connection, and the battery pack has a nominal voltage of 14 V, when charging the battery pack, the converter is operated as buck, and when discharging the battery pack, the converter is operated as boost.
Further preferably, the buck/boost converter comprises a first switch connected in series between the input and output side. Further preferably, the buck/boost converter comprises an inductance in series with the first switch. Further preferably, the buck/boost converter comprises a second switch connected between the first switch and the inductance. Further preferably, the buck/boost converter comprises capacities each connected in parallel with the input and output side. Preferably, the resistor of the buck/boost DC sensing unit is connected in series between the output side and the input side. Preferably, the buck/boost converter comprises a bidirectional blocking circuit connected in series between the input side and the output side. Thereby, preferably, for instance in case of malfunction, the input side and the output side can be disconnected from one another.
The present disclosure also concerns a buck/boost conversion device. The buck/boost conversion device comprises a bidirectional buck/boost converter and the control circuit according to any one of the foregoing described preferable configurations. Therein, the control circuit is configured to control the buck/boost converter so as to buck a voltage input into the buck/boost conversion device or so as to boost a voltage output by the buck/boost conversion device.
Preferably, the buck/boost converter comprises a first switch and a second switch. Therein, for example in buck mode, the second switch is driven with the synchronous rectification signal so as to function as a diode of the buck/boost converter, and the first switch is driven with the even inverted PWM control signal so as to function, together with at least one inductance of the buck/boost converter, as a voltage buck, or vice-versa in boost mode based on the mode of operation. For instance, in the boost mode, the second switch is preferably driven with the even inverted PWM control signal while the first switch is driven with the odd inverted synchronous rectification signal.
Further preferably, the buck/boost conversion device is connected to a battery pack comprising at least one battery.
Advantageously, the buck/boost conversion device further comprises a bidirectional blocking circuit, especially in series with the battery pack. Preferably, the bidirectional blocking circuit is a back-to-back ORing. For example, the back-to-back ORing comprises two switches connected in anti-series with one another. The bidirectional blocking circuit further provides the advantage that input and output side of the buck/boost converter can be disconnected from one another, especially for instance in case of a malfunction, or for example in case of an output overvoltage event.
Preferably, the buck/boost conversion device comprises a plurality of bidirectional buck/boost converters and a plurality of control circuits according to any one of the foregoing described preferable configurations. Preferably therein, each of the buck/boost converters comprises a respective output respectively connected to one or more batteries. Further preferably, the plurality of buck/boost converters are connected in common, especially in parallel, to an input side, particularly an input bus. For example, the plurality of buck/boost converters are connected in common to a 24 V bus connection and are each connected to a battery or battery pack with, for example, a nominal voltage of 14 V. Advantageously, in the preferable case that one or more, preferably all, such connected buck/boost converters and their respective control circuits comprise the shunt resistance, current balancing may be achieved between the batteries/battery packs.
Further details, advantages, and features of the preferred embodiments of the present disclosure are described in detail with reference to the figures. Therein:
The bidirectional buck/boost converter 2 (henceforth “the converter 2”) will be firstly described. The converter 2 according to the present embodiment comprises a bus connection 101, for example for connection with mains and/or an external power supply, as an input. Further, the converter 2 comprises an output side connection 102, for example for connection with a battery pack. In the present embodiment, the bus connection 101 is connected with mains and the output side connection 102 is connected to a battery pack. Preferably, the mains is a 24 V source. A nominal voltage of the battery pack is for example 14 V. Therefore, the converter 2 boosts or bucks the voltages between the input side 101 and the output side 102 depending on whether the battery pack is being charged (buck mode) or is being discharged (boost mode).
For ease of explanation, in the following, “input” will be referred to as the input side bus connection 101 during buck mode. It however goes without saying that during boost mode, “input” may be the “output” at the output side 102 of the buck mode, since for example the battery pack inputs energy into the converter 2 during discharge, and vice versa.
Further, the converter 2 comprises a first switch 103 connected in series between the bus connection 101 and the output side connection 102. The converter 2 comprises an inductance 105 in series with the first switch 103.
The converter 2 comprises a second switch 104 connected between the first switch 103 and the inductance 105. Further, the converter 2 comprises capacities 106, 107 respectively connected in parallel with the bus connection 101 and the output side connection 102.
The first switch 103 and the second switch 104 are respectively MOSFETs.
The converter 2 comprises a bidirectional blocking circuit 108 connected in series between the bus connection 101 and the output side connection 102. Thereby, preferably, for instance in case of malfunction, the input side and the output side of the converter 2 can be securely disconnected from one another.
Further in view of
The control circuit 1 comprises a buck/boost detection unit 3 configured to detect and output a mode of operation of the bidirectional buck/boost converter selected from buck mode and boost mode. In the present embodiment, the buck/boost detection unit 3 is configured to receive a command signal from an external system controller 200. The command signal indicates whether the converter 2 is to be driven in buck mode or boost mode. For instance, the command signal is based on charge status of the battery pack, or whether for example a mains failure has taken place. An exemplary embodiment in which the buck/boost detection unit 3 is configured to output the mode of operation based on detection, i.e. not based (entirely or solely) on an external command signal, will be discussed with respect to
Further, the control circuit 1 comprises a voltage/current regulator unit 4 configured to receive the mode of operation output from the buck/boost detection unit 3 and configured to output a corresponding regulating signal based on the mode of operation.
The voltage/current regulator unit 4 comprises a buck regulator subunit 5 and a boost regulator subunit 6, which will be described in detail below.
Furthermore, the control circuit 1 comprises a PWM (Pulse Width Modulation) control unit 7 configured to receive the regulating signal from the voltage/current regulator unit 4 and configured to output a PWM control signal based on the regulating signal.
The control circuit 1 comprises a gate drive signal toggle unit 8 configured to receive the PWM control signal and the mode of operation and configured to generate and output gate drive signals for driving switching operations of the switches 103, 104 of the converter 2 based on the mode of operation and on the PWM control signal.
As can be taken from
Further, the control circuit 1 comprises a high-side/low-side driver unit 9 configured to receive the gate drive signals output from the gate drive signal toggle unit 8 and configured to amplify the gate drive signals and output the amplified gate drive signals to the switches 103, 104.
In the present embodiment, the gate drive signal toggle unit 8 outputs a relatively low voltage signal, for example 5 V at roughly 10 mA. The PWM control signal output by the PWM control unit 7 is for example roughly 12 V to 15 V. Therefore, the gate drive signals output by the gate drive signal toggle unit 8 are amplified by the high-side/low-side driver unit 9, preferably to a current of roughly one to multiple amp (A), so as to quickly drive the switches 103, 104, especially so as to overcome a gate resistance of the switches 103, 104.
The control circuit 1 further comprises current sensing units 10, 11. A first current sensing unit 10 is connected in series with the first switch 103. The first current sensing unit 10 especially senses a (non-zero) current during buck mode operation.
A second current sensing unit 11 is connected in series with the second switch 104. The second current sensing unit 11 especially senses a (non-zero) current during boost mode operation.
Further, the first and second current sensing units 10, 11 are each connected to a current sense toggle unit 12. The current sense toggle unit 12 is configured to receive a current value output by each of the current sensing units 10, 11.
Further, as can be taken from
The PWM control unit 7 uses the input current value from the current sense toggle unit 12 for generating and regulating the PWM control signal, which is then output to the gate drive signal toggle unit 8.
In particular, the PWM control unit 7 is configured to compare the regulated signal from the voltage/current regulator unit 4 with the current signal from the current sense toggle unit 12, i.e. with the signal from one of the current sensing units 10, 11. The PWM control unit 7 outputs the PWM control signal based on this comparison. Thereby, preferably, the PWM control unit 7 is configured to perform peak current mode modulation based on said regulated signal and based on the input current signal from the current sense toggle unit 12 from the current sensing units 10, 11.
The control circuit 1 comprises a buck/boost DC sensing unit 13.
The buck/boost DC sensing unit 13 is configured to sense a current output by and/or flowing through the converter 2 and is configured to feed the sensed current back to the voltage/current regulator unit 4. The buck/boost DC sensing unit 13 comprises a resistor 14, especially a shunt resistor, for measuring the current. As can be taken from
Preferably, the buck/boost DC sensing unit 13 comprises two outputs 15, 16. A first output 15 is preferably configured to output a current value during buck mode (henceforth “buck out signal”). A second output 16 is preferably configured to output a current value during boost mode (henceforth “boost out signal”).
Therein, the buck/boost DC sensing unit 13 is preferably configured such that the first output 15 only outputs a current value during buck mode, and such that the second output 16 only outputs a current value during boost mode.
The voltage/current regulator unit 4 is configured to regulate the voltage and/or current regulating signal based on the fed back sensed current. More specifically, the voltage/current regulator unit 4 is configured to regulate the voltage and/or current regulating signal based on the aforementioned buck out or boost out signals. The voltage/current regulator unit 4 is also configured to regulate the voltage and/or current regulating signal based on sensed voltage values at the input side (bus connection 101) and at the output side 102 (battery pack).
For this, the control circuit 1 further comprises a first voltage sensing unit 22, which is configured to sense a voltage at the bus connection 101. Further, the control circuit 1 comprises a second voltage sensing unit 23, which is configured to sense a voltage at the output side connection 102 (herein, the battery pack).
The voltage/current regulator unit 4 comprises a buck regulator subunit 5 and a boost regulator subunit 6, as mentioned above. Each buck/boost subunit 5, 6 preferably comprises an input for receiving the respective buck out or boost out signal from the respective output 15, 16 of the buck/boost DC sensing unit 13.
The buck regulator subunit 5 is de-activated by a non-zero boost out signal, and the boost regulator subunit 6 is de-activated by a non-zero buck out signal, which will be explained below. Further as demonstrated in
Each of the buck regulator subunit 5 and the boost regulator subunit 6 are configured to output a regulated current and a regulated voltage. Further, the buck/boost detection unit 3 also outputs the operation mode (being boost active or buck active signals) to the buck regulator subunit 5 and the boost regulator subunit 6.
Further, the voltage value sensed by the second voltage sensing unit 23 is input to the voltage/current regulator unit 4, more specifically to the buck subunit 5 thereof. The voltage value sensed by the first voltage sensing unit 22 is input to the voltage/current regulator unit 4, more specifically to the boost subunit 6 thereof. Therein, the voltage/current regulator unit 4 is configured to regulate the current/voltage output to the PWM control unit 7 based additionally on the sensed voltage values from the first and second voltage sensing units 22, 23.
Therein, each subunit 5, 6 is configured to output the regulated voltage based on a comparison of an external reference signal (indicating, for instance, a target voltage value) from for instance the external system controller 200 with the respective voltage value output by the respective voltage sensing unit 22, 23. The boost regulator subunit 6 is configured to receive the voltage value at the input side 101 from the first voltage sensing unit 22, and the buck regulator subunit 5 is configured to receive the voltage value at the output side 102, from the second voltage sensing unit 23. In other words, each subunit 5, 6 preferably compares the target voltage value given by the reference signal with the generated value fed back from the voltage sensing units 22, 23 during voltage regulation.
Further, each respective subunit 5, 6 is configured to be de-activated when the respective (the oppositely respective) active signal (buck active or boost active) from the buck/boost detection unit 3 is non-zero such that said respective subunit 5, 6 does not output a regulated voltage.
Further therein, each subunit 5, 6 is also configured to output the regulated current based on a comparison of the external reference signal with the respective buck out or boost out current signal from the buck/boost DC sensing unit 13. Herein, the reference signal for instance indicates a target current value for the converter 2. In other words, the buck regulator subunit 5 for instance compares the external reference signal with the buck out signal (being the current signal from the buck/boost DC sensing unit 13 during buck mode) and outputs the regulated current based thereon. The same holds correspondingly true for the boost regulator subunit 6 with the boost out signal.
In other words, voltage regulation is activated and de-activated via the buck active or boost active signals from the buck/boost detection unit 3, whereas current regulation is activated and de-activated via the buck out or boost out signals from the buck/boost DC current sensing unit 13.
Therefore, the voltage/current regulator unit 4 comprises an input for buck out current signal and an input for reference current (buck regulator subunit 5 current regulation), an input for boost active signal, an input for reference voltage, and an input for the respectively sensed voltage value (buck regulator subunit 5 voltage regulation), an input for boost out current signal and an input for reference current (boost regulator subunit 6 current regulation), an input for buck active signal, an input for reference voltage, and an input for the respectively sensed voltage value (boost regulator subunit 6 voltage regulation).
Based on these input signals, the voltage/current regulator unit 4 outputs a current/voltage regulating signal to the PWM control unit 7. As mentioned above, the PWM control unit 7 outputs the PWM control signal based on the regulating signal to the gate drive signal toggle unit 8, which will now be explained in view of
Therein, as can be seen on the left side of
The PWM control signal is input into a first inverter 17. Preferably, the first inverter 17 is a Schmitt trigger. Thereby, the PWM control signal (in addition to threshold properties) is inverted. The inverted PWM control signal is then input into a second inverter 18, which is preferably also a Schmitt trigger. The inverted PWM control signal is thus twice-inverted via the second inverter 18.
The twice-inverted PWM control signal is essentially used to drive one of the switches 103, 104 so as to voltage boost or voltage buck, depending on the mode of operation. Essentially, the once-inverted PWM control signal is used to drive the other switch 104, 103 in accordance with synchronous rectification, essentially as a diode opposing the driving of the one switch 103, 104.
As can be taken from the dotted lines in
In the present embodiment, the once-inverted PWM control signal (from the first inverter 17) is input, in parallel to the second inverter 18, into an on-time-duration limitation unit 19. The on-time duration limitation unit 19 is configured to limit a time-duration of one of the gate drive signals to a maximum threshold value. Therein, the on-time-duration limitation unit 19 is configured to set said gate drive signal(s) to low when the on-time-duration of the gate drive signal reaches the maximum threshold value. Thereby, a scenario is avoided in which the PWM control unit 7 is turned off, thereby constantly outputting low, and the gate drive signal toggle unit 8 thus constantly outputting high (via the inversion), which would otherwise damage the converter 2 and/or specifically the switches 103, 104 thereof.
Preferably, the maximum threshold value is a time value. Preferably, the maximum threshold value is roughly equal to (or rather an inversion of) a switching frequency of the converter 2. For example, the maximum threshold value is set to roughly 10 μs at an exemplary switching frequency of 100 KHz.
Further in view of
The buck/boost mode selection logic unit 20 is connected to or comprises the input for the mode of operation signal output by the buck/boost detection unit 3 (right side of
The buck/boost mode selection logic unit 20 outputs the two PWM control signals to a dead-time generation unit 21, which generates a dead-time between the two PWM control signals before outputting these to the respective switches 103, 104 via the high-side/low-side driver unit 9. The generated dead-time is preferably roughly 200 ns.
Thus, the high-side/low-side driver unit 9 outputs the once-inverted PWM control signal and the twice-inverted PWM control signal, along with maximum on-duration being limited and dead-time being generated therebetween, to the switches 103, 104, to thereby drive the converter 2.
As stated shortly above, in the second embodiment, in addition or alternatively to the command signal (boost or buck mode) being output by a system controller 200, in the present embodiment, the buck/boost detection unit 3 is configured to output the mode of operation based on detection within the converter 2 as follows.
Herein, the control circuit 1 comprises a comparator logic module 24.
The comparator logic module 24 is configured to compare voltage values between the bus connection 101 and the output side connection 102. The comparator logic module 24 outputs a signal based on the comparison to the buck/boost detection unit 3.
For instance, in case the comparator logic module 24 senses a voltage, for example 24 V, at the bus connection 101, the comparator logic module 24 outputs a signal (for instance a high signal) indicating “buck” mode, corresponding to for example charging the battery pack (nominal voltage rating 14 V, for example). On the other hand, in case the comparator logic module 24 senses no voltage at the bus connection 101, and senses a voltage at the output side connection 102, the comparator logic module 24 is configured to output a signal (for instance a low signal) indicating “boost” mode, corresponding to for example discharging the battery pack (boosting the 14 V of the battery pack to 24 V).
As indicated in
In the foregoing embodiments, at least the PWM control unit 7 and the gate drive signal toggle unit 8 are separate components, especially separate integrated circuits. In other words, preferably, the foregoing described functions and configurations of at least the PWM control unit 7 and the gate drive signal toggle unit 8 are not achieved by a single PWM controller. In the present embodiments, the PWM control unit 7 is preferably single-ended.
Further, preferably, the buck/boost conversion device 100 comprises the foregoing explained components of the bidirectional buck/boost converter 2 and the control circuit 1.
Specifically,
As shown in
Furthermore, as explained above with respect to
In general, during boost mode, each boost regulator subunit 6 (compare
In other words, current is balanced between the buck/boost conversion devices 100 via the paralleled module connection shown in
In addition to the foregoing written explanations, it is explicitly referred to
| Number | Date | Country | Kind |
|---|---|---|---|
| 22212913.2 | Dec 2022 | EP | regional |
