Patent Application
20060039408
1. Field of the Invention
This invention relates generally to the field of digital interface design and, more particularly, to bus interface design.
2. Description of the Related Art
Many digital systems, especially those that include high-performance, high-speed circuits, are prone to operational variances due to temperature effects. This presents a need to implement thermal management and control in many of those systems. Devices that monitor temperature and voltage are often included in order to perform the required thermal management/control, and thus maintain the integrity of the system components. Personal computers (PC), signal processors and high-speed graphics adapters, among others, typically benefit from such thermal management circuits. For example, a central processor unit (CPU) that typically “runs hot” as its operating temperature reaches high levels may require a temperature sensor in the PC to insure that it doesn't malfunction or break due to thermal problems. Sensors may be used to monitor a variety of parameters and may be configured at numerous specified locations within a system. Data received and/or recorded by the sensors is typically transmitted to a processing/control unit that analyzes and uses the data in order to determine what if any action is necessary to maintain reliable and stable system operation. Often, when monitoring thermal responses for protecting systems from possible thermal damage, thermal sensor information is directly provided to hardware logic circuits (failsafe circuits) to increase reliability over software solutions.
Thermal management systems often include fans used in controlling the temperature in the operating environment of system components. Typically, personal computers (PCs) are equipped with a CPU fan and one or more case fans. A remote thermal diode may be integrated on the CPU and may be used by a sensor circuit to capture the temperature of the CPU. A thermal sense diode is often integrated within the sensor circuit where it is typically used to capture ambient temperatures. Current implementations of thermal management systems include integrated digital and analog solutions, which typically lack flexibility due to the difficulties encountered with analog signal routing, and stand-alone solutions that provide higher accuracies and route easier, but are generally more expensive.
One typical approach is to use the System Management Bus (SMBus)—first defined by Intel Corporation in 1995—to connect hardware monitors to the host controller. In many present thermal management systems the sensors typically communicate over the two-wire SMBus and rely on a host to program them and to control them. The SMBus generally has a large number of devices connected to it, from simple temperature sensors to complex management chips, even system memory Dual Inline Memory Modules (DIMMs). Furthermore, more and more features have been added in the sensors, such as thermal trip points, programmable data formats for the temperature data, and programmable conversion rates among others. These features generally result in added digital circuits, affecting the physical layout of IC solutions. Typically, a portion of the silicon area of the sensor circuit is consumed by digital circuitry, the remaining portion by analog sensor components. In addition, being coupled to a large number of devices inevitably results in increasing traffic to the SMBus. The increased traffic leads to an increase in the time required to power up the PC (i.e. extended boot time), and to more complex debugging issues. The SMBus is also prone to occasional loss of communication and may therefore not provide sufficient reliability for certain management applications.
Another approach is to integrate the analog functions together into a single chip in order to save costs and to avoid congestion of the SMBus. Integration solutions however typically result in other problems. It is generally difficult and time consuming to route sensitive analog signals to the chip, and the options for placement of the sensor(s) may also become severely limited. Because of the difficulty in routing all the required connections on PC motherboards, much attention has been given to one-wire communication solutions.
A common system component that incorporates a variety of functions and is typically employed in thermal management systems is the Super I/O (SIO) controller. The Super I/O controller is a single chip, which performs many functions that were previously performed by several pieces of hardware, providing the benefits of design standardization and simplification and thus a reduction in cost. A Super I/O chip is typically responsible for controlling the slower-speed peripherals found in a PC. Standard devices that are virtually the same on every PC make it is possible (and easier) to integrate many control functions into a commodity chip instead of having to consider them for each motherboard design. (Serial port control, parallel port control, floppy disk control). In addition, embedded μControllers and chipset components are also occasionally employed as host/controller devices configured to receive system and/or sensor information, and provide system management functions.
One single-wire protocol that may couple to an SIO device uses ratiometric signaling, where the sensor transmits temperature data by accurately controlling the duty cycle (ratio of pulse width and period) of a square wave. That is, the output of the sensor is in effect a Pulse Width Modulated (PWM) digital signal, where data is coded in the duty cycle of the signal. This solution generally requires substantial processing to be performed by the host in order to extract the data from the duty cycle. For example, the SIO device may need to include a multiplier to convert the ratio received to a standard sensor reading. Ratiometric solutions are also susceptible to noise, typically presenting reliability problems.
Another single-wire protocol is the SensorPath bus introduced by National Semiconductor, which was designed specifically to alleviate some of the problems associated with thermal management systems. The SensorPath bus isolates temperature and voltage data onto a dedicated bus that is more optimized to the purpose, enabling both independent and centralized control of the thermal management system. The bus uses a single wire to connect the SIO device and the sensor and provides a digital interface, simplifying board design and easing placement of components. While the SensorPath bus offers a single-wire solution, it employs a substantially complicated protocol, making a seamless configuration of a thermal management system with the SensorPath bus relatively difficult.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with embodiments of the present invention as described herein.
Various embodiments of the invention comprise a bus and bus protocol (referred to as Budget Sensor Bus, or BBUS) that can provide a low cost, highly reliable, single pin connection to transmit information from any one of many different device types to any one of many different host types. The transmitted information may include system status, configuration or management data such as CPU type and/or ID, memory size or type, docking type or ID, information about the presence of optional components and ambient light or noise levels, temperature measurements and voltage measurements, among others.
In one set of embodiments, the BBUS couples a sensor circuit to a host, where data transmission over the BBUS is regulated according to a BBUS bus protocol. The sensor circuit may include up to eight temperature sensors, each temperature sensor operable to provide temperature data indicative of a corresponding measured temperature, and up to eight voltage sensors, each voltage sensor operable to provide voltage data indicative of a corresponding measured voltage. In one embodiment, the BBUS directly transmits raw data bits from any respective sensor in the sensor circuit to the host, and uses a pre-amble to “teach” the host what bit frequency is used by the respective sensor. After the pre-amble, the host may get in sync and may be enabled to directly read the data bits that follow. The BBUS may provide a means for the sensor to immediately transfer temperature conversions to the host.
In another set of embodiments, the BBUS may be used to transmit system information from any monitored device in the system in place of either voltage or temperature information, such as system configuration or device identification information, which may be used to more effectively manage the system. For example, one or more CPU's may be connected to a system logic device (for example a Southbridge). The one or more CPU's may transmit CPU type, cache size, revision number, thermal limitation, or other management information via the BBUS. Based on the transmitted information the system logic may be operable to set up a single CPU or multiple CPU system for proper operation with proper operating limits.
In one embodiment, the BBUS is a point-to-point dedicated bus allowing the system logic to recognize the type of any connected device, and/or to be informed by that device at system reset. The BBUS may function to help system logic configure system operation both by the presence or absence of a connected device on a specific pin, and by the data transmitted over that pin. All functions and operations required for interpreting temperature/voltage data, and/or system configuration/device identification data may reside within the host. In one embodiment, the BBUS may transmit data from a sensor/monitored device to a host, but not from the host to the sensor/monitored device.
In one set of embodiments the BBUS protocol features three main states: Reset (or Power Down State), Active State, and Inactive State, and transmits packets of information. Packets may be transmitted in NRZ format, and each packet may comprise a start sequence, a data type identifier, a device number or a register number identifier, information data, and a stop sequence. Each sequence and identifier, as well as the information data may comprise a determined number of bits. For example, in one embodiment each packet comprises a three-bit start sequence, one sensor-type bit, a three-bit sensor number, eleven-bit sensor data and one stop bit.
Thus, the BBUS provides a more cost effective thermal sensing and/or system management solution, being a single-wire bus implementing a substantially simple protocol, while minimizing required digital circuitry within the sensor circuit (or any other selected monitored circuit) and also minimizing any additional burden on the host device. In one set of embodiments, the BBUS operates as a low speed, reliable management bus that is low cost due to both its implementation and single pin design.
The foregoing, as well as other objects, features, and advantages of this invention may be more completely understood by reference to the following detailed description when read together with the accompanying drawings in which:
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. Note, the headings are for organizational purposes only and are not meant to be used to limit or interpret the description or claims. Furthermore, note that the word “may” is used throughout this application in a permissive sense (i.e., having the potential to, being able to), not a mandatory sense (i.e., must).” The term “include”, and derivations thereof, mean “including, but not limited to”. The term “coupled” means “directly or indirectly connected”.
In addition to the single-wire interface, BBUS 110 may additionally feature point-to-point data transmission, 3.3 Volt signaling, and an operating frequency of 100 KHz±20%. In one embodiment, BBUS 110 supports up to eight sensors, and employs a data format that supports measured temperature ranges of −63.875° C. to 191.875° C. The up to eight sensors of each type (temperature and voltage) supported by BBUS 110 may be configured in a single sensor block or sensor Integrated Circuit (IC) to support the single-wire interface. BBUS 110 may also allow the sensors that are coupled to BBUS 110 to be placed in a low power mode. In one set of embodiments the BBUS protocol features three main states: Reset (or Power Down State), Active State, and Inactive State.
The Power Down state may be used by SIO controller device 102 to place sensor circuit 104 in a low power state or to put sensor circuit 104 on hold when SIO controller device 102 cannot accept more data. The Power Down state may be initiated by SIO controller device 102 by driving and holding a low state on the bus. SIO controller device 102 may also force the bus into the Power Down state if the bus is in the Inactive state. Sensor circuit 104 may be responsible for detecting the Power Down state when sensor circuit 104 is the Inactive state. SIO controller device 102 may be required to drive the bus high for one clock cycle (which may be of a 100 kHz±20% frequency) before releasing the bus when exiting the Power Down state.
The Inactive state may be designated the default bus state when no data is being transferred. In one embodiment, the Inactive state is characterized by the bus not being driven by either sensor circuit 104 or SIO controller device 102. An internal weak pull-up resistor may be configured on SIO controller device 102 to hold the bus in a high state.
The Active state may be used by sensor circuit 104 to transmit sensor data. In this state the sensor may transmit nineteen bits of data to SIO control device 102 and then return the bus to the Inactive state. Sensor circuit 104 may enter the Active State sixteen clock cycles (which may be of a 100 kHz±20% frequency) after the bus enters the Inactive state. When the bus is in the Inactive state, both sensor circuit 104 and SIO controller device 102 may be required to have their output drivers in a high impedance state.
As previously mentioned, BBUS 110 may transmit packets of information.
In one embodiment, temperature data (sensor data 208 when sensor type bit 204 is set to indicate temperature data) is transmitted in two's complement form with a decimal offset of 64. Bits 10-3 of sensor data 208 may represent the whole number portion of the temperature value while bits 2-0 of sensor data 208 may represent the fractional portion of the temperature value. An actual temperature reading may be determined by adding 64 to the whole number portion of the temperature measurement.
Voltage data (sensor data 208 when sensor type bit 204 is set to indicate voltage data) may be transmitted in 10-bit or 8-bit binary form with bit 10 being a reserved bit. In 8-bit binary format, bits ‘0’ and ‘1’ may be set to zero. In one set of embodiments where sensor circuit 104 comprises an analog to digital converter (ADC), the actual measured voltage value may be determined by the following formula:
VMeasurement=(Vref*Sensor Reading)/1024 (1)
where Vref is the reference voltage used by the ADC, and the Sensor Reading represents the decimal equivalent of the binary data transmitted sensor circuit 104. The table of
In one set of embodiments, sensor circuit 104 may be required to restart conversions beginning with sensor number 206 set to 000, that is, from designated sensor number zero, upon exiting the Power Down state. Sensor circuit 104 may also be required to transmit temperature conversion/voltage data to SIO controller device 102 over BBUS 110 in sensor number order. In one embodiment, sensor circuit 104 assigns sensor numbers to all enabled sensors sequentially starting from zero and without skipping any numbers. For example, if sensor circuit 104 contains five enabled sensors, the five sensors may receive sensor numbers zero through four.
In order to reduce the risk of bus contention, in one set of embodiments SIO controller device 102 may be required to initiate the Power Down state during a required inactive time between packets, or place BBUS 110 in a low state using an integrated, weak pull-down resistor. In order to reduce power, SIO controller device 102 may also integrate a pull-up resistor that may be used on BBUS 110, and disable the pull-up resistor when placing a sensor in Power Down mode. SIO controller device 102 may also be required to implement a Schmitt trigger input as an input cell on BBUS 110.
While the packets above are described for sensor circuit 104, as previously indicated, instead of sensor circuit 104 alternate devices and/or circuits may be monitored through BBUS 110, such as an embedded processor or CPU, with BBUS 110 coupling the alternate device to various system logic, for example a Southbridge in lieu of SIO controller device 102.
Although the embodiments above have been described in considerable detail, other versions are possible. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications. Note the section headings used herein are for organizational purposes only and are not meant to limit the description provided herein or the claims attached hereto.
