BUFFER AMPLIFIER FOR SOURCE DRIVER

Abstract

A buffer amplifier for source driver is disclosed. The buffer amplifier has an N-channel differential amplifier and a P-channel differential amplifier as its input stages so as to achieve rail-to-rail input, and a class AB amplifier to push-pull the output stage so as to achieve rail-to-rail output. The output stage of the buffer amplifier is capable of larger charge/discharge, is faster, and has equal charge/discharge time. More importantly, the buffer amplifier has advantages such as lower power consumption, higher slew rate, and a more stable output.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a circuit diagram of a conventional reference voltage generator.

FIG. 2 is a circuit diagram of a buffer amplifier for source driver according to an embodiment of the present invention.

FIG. 3 is a detailed circuit diagram of the buffer amplifier for source driver in FIG. 2 according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a buffer amplifier for source driver according to another embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of the buffer amplifier for source driver in FIG. 4 according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of a buffer amplifier for source driver according to yet another embodiment of the present invention.

FIG. 7 is a detailed circuit diagram of the buffer amplifier for source driver in FIG. 6 according to the yet another embodiment of the present invention.

Claims

1. A buffer amplifier for source driver, comprising: a first type differential amplifier, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is for receiving an input signal;a second type differential amplifier, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is for receiving the input signal, and the negative input terminal is coupled to the negative input terminal of the first type differential amplifier;a 1st transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the output terminal of the first type differential amplifier, and the first source/drain is coupled to a first power cord;a 2nd transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a first bias, and the first source/drain is coupled to the second source/drain of the 1st transistor;a 3rd transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a second bias, the first source/drain is coupled to the second source/drain of the 1st transistor, and the second source/drain is coupled to the second source/drain of the 2nd transistor;a 4th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the output terminal of the second type differential amplifier, the first source/drain is coupled to the second source/drain of the 2nd transistor, and the second source/drain is coupled to a second power cord;a 5th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the first source/drain of the 2nd transistor, the first source/drain is coupled to the first power cord, and the second source/drain is coupled to the negative input terminal of the first type differential amplifier; anda 6th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the second source/drain of the 2nd transistor, the first source/drain is coupled to the second power cord, and the second source/drain is coupled to the negative input terminal of the first type differential amplifier.

2. The buffer amplifier as claimed in claim 1, wherein the 1st transistor, the 2nd transistor, and the 5th transistor are P-type metal oxide semiconductor field effect transistors (PMOSFET).

3. The buffer amplifier as claimed in claim 1, wherein the 3rd transistor, the 4th transistor, and the 6th transistor are N-type metal oxide semiconductor field effect transistors (NMOSFET).

4. The buffer amplifier as claimed in claim 1, wherein the input stage differential pair of the first type differential amplifier is a NMOSFET, and the input stage differential pair of the second type differential amplifier is a PMOSFET.

5. The buffer amplifier as claimed in claim 4, wherein the first type differential amplifier comprises: an N-type differential pair, comprising: a 7th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the positive input terminal of the first type differential amplifier; andan 8th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the negative input terminal of the first type differential amplifier, the first source/drain is coupled to the first source/drain of the 7th transistor, the second source/drain is the output terminal of the first type differential amplifier; anda 9th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, the gate and the second source/drain are coupled to the second source/drain of the 7th transistor;a 10th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, the gate and the second source/drain are coupled to the second source/drain of the 8th transistor; anda 11th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a third bias, the first source/drain is coupled to the first source/drain of the 7th transistor, and the second source/drain is coupled to the second power cord.

6. The buffer amplifier as claimed in claim 5, wherein the second type differential amplifier comprises: a 12th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a fourth bias, the first source/drain is coupled to the first power cord;a 13th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, and the gate is coupled to the gate of the 9th transistor;a P-type differential pair, comprising: a 14th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the positive input terminal of the second type differential amplifier, the first source/drain is coupled to the second source/drain of the 12th transistor; anda 15th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the negative input terminal of the second type differential amplifier, the first source/drain is coupled to the second source/drain of the 12th transistor, the second source/drain is coupled to the second source/drain of the 13th transistor and is the output terminal of the second type differential amplifier; anda 16th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate and the second source/drain are coupled to the second source/drain of the 14th transistor, and the first source/drain is coupled to the second power cord;a 17th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate and the second source/drain are coupled to the second source/drain of the 15th transistor, and the first source/drain is coupled to the second power cord; andan 18th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the gate of the 16th transistor, the first source/drain is coupled to the second power cord, and the second source/drain is coupled to the second source/drain of the 8th transistor.

7. The buffer amplifier as claimed in claim 6, wherein the 7th, 8th, 11th, 16th, 17th, and the 18th transistors are NMOSFETs, and the 9th, 10th, 12th, 13th, 14th, and the 15th transistors are PMOSFETs.

8. The buffer amplifier as claimed in claim 1, further comprising: a first capacitor, having one terminal coupled to the second source/drain of the 5th transistor, and another terminal coupled to the gate of the 5th transistor; anda second transistor, having one terminal coupled to the second source/drain of the 6th transistor, and another terminal coupled to the gate of the 6th transistor.

9. A buffer amplifier for source driver, comprising: a first type differential amplifier, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is for receiving an input signal;a second type differential amplifier, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal is for receiving the input signal, and the negative input terminal is coupled to the negative input terminal of the first type differential amplifier;a 1st transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the output terminal of the first type differential amplifier, and the first source/drain is coupled to a first power cord;a 2nd transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a first bias, and the first source/drain is coupled to the second source/drain of the 1st transistor;a 3rd transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a second bias, and the first source/drain is coupled to the second source/drain of the 2nd transistor;a 4th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the output terminal of the second type differential amplifier, the first source/drain is couple d to the second source/drain of the 3rd transistor, and the second source/drain is coupled to a second power cord;a 5th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the first source/drain of the 2nd transistor, the first source/drain is coupled to the first power cord, the second source/drain is coupled to the negative input terminal of the first type differential amplifier; anda 6th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the second source/drain of the 3rd transistor, the first source/drain is coupled to the second power cord, and the second source/drain is coupled to the negative input terminal of the first type differential amplifier.

10. The buffer amplifier as claimed in claim 9, wherein the 1st transistor, the 3rd transistor, and the 5th transistor are PMOSFETs.

11. The buffer amplifier as claimed in claim 9, wherein the 2nd transistor, the 4th transistor, and the 6th transistor are NMOSFETs.

12. The buffer amplifier as claimed in claim 9, wherein the input stage differential pair of the first type differential amplifier are NMOSFETs, and the input stage differential pair of the second type differential amplifier are PMOSFETs.

13. The buffer amplifier as claimed in claim 12, wherein the first type differential amplifier comprises: an N-type differential pair, comprising: a 7th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the positive input terminal of the first type differential amplifier; andan 8th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the negative input terminal of the first type differential amplifier, the first source/drain is coupled to the first source/drain of the 7th transistor, and the second source/drain is the output terminal of the first type differential amplifier; anda 9th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, and the gate and the second source/drain are coupled to the second source/drain of the 7th transistor;a 10th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, and the gate and the second source/drain are coupled to the second source/drain of the 8th transistor; anda 11th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a third bias, the first source/drain is coupled to the first source/drain of the 7th transistor, and the second source/drain is coupled to the second power cord.

14. The buffer amplifier as claimed in claim 13, wherein the first type differential amplifier comprises: a 12th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a fourth bias, and the first source/drain is coupled to the first power cord;a 13th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, and the gate is coupled to the gate of the 9th transistor;a P-type differential pair, comprising: a 14th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the positive input terminal of the second type differential amplifier, and the first source/drain is coupled to the second source/drain of the 12th transistor; anda 15th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the negative input terminal of the second type differential amplifier, the first source/drain is coupled to the second source/drain of the 12th transistor, the second source/drain is coupled to the second source/drain of the 13th transistor and is the output terminal of the second type differential amplifier; anda 16th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate and the second source/drain are coupled to the second source/drain of the 14th transistor, and the first source/drain is coupled to the second power cord;a 17th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate and the second source/drain are coupled to the second source/drain of the 15th transistor, and the first source/drain is coupled to the second power cord; andan 18th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the gate of the 16th transistor, the first source/drain is coupled to the second power cord, and the second source/drain is coupled to the second source/drain of the 8th transistor.

15. The buffer amplifier as claimed in claim 14, wherein the 7th, 8th, 11th, 16th, 17th, and the 18th transistors are NMOSFETs, and the 9th, 10th, 12th, 13th, 14th, and the 15th transistors are PMOSFETs.

16. The buffer amplifier as claimed in claim 9 further comprising a capacitor, having one terminal coupled to the second source/drain of the 5th transistor and another terminal coupled to the second source/drain of the 2nd transistor.

17. A buffer amplifier for source driver, comprising: a first type differential amplifier, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal receives an input signal;a second type differential amplifier, having a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal receives the input signal, and the negative input terminal is coupled to the negative input terminal of the first type differential amplifier;a 1st transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the output terminal of the first type differential amplifier, and the first source/drain is coupled to a first power cord;a 2nd transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the second source/drain of the 1st transistor;a 3rd transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain and the gate are coupled to the second source/drain and the gate of the 2nd transistor;a 4th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the output terminal of the second type differential amplifier, the first source/drain is coupled to the second source/drain of the 3rd transistor, and the second source/drain is coupled to a second power cord;a 5th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the first source/drain of the 2nd transistor, the first source/drain is coupled to the first power cord, and the second source/drain is coupled to the negative input terminal of the first type differential amplifier; anda 6th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the second source/drain of the 3rd transistor, the first source/drain is coupled to the second power cord, and the second source/drain is coupled to the negative input terminal of the first type differential amplifier.

18. The buffer amplifier as claimed in claim 17, wherein the 1st transistor, the 3rd transistor, and the 5th transistor are PMOSFETs.

19. The buffer amplifier as claimed in claim 17, wherein the 2nd transistor, the 4th transistor, and the 6th transistor are NMOSFETs.

20. The buffer amplifier as claimed in claim 17, wherein the input stage differential pair of the first type differential amplifier are NMOSFETs, and the input stage differential pair of the second type differential amplifier are PMOSFETs.

21. The buffer amplifier as claimed in claim 20, wherein the first type differential amplifier comprises: an N-type differential pair, comprising: a 7th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the positive input terminal of the first type differential amplifier; andan 8th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the negative input terminal of the first type differential amplifier, the first source/drain is coupled to the first source/drain of the 7th transistor, and the second source/drain is the output terminal of the first type differential amplifier; anda 9th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, and the gate and the second source/drain are coupled to the second source/drain of the 7th transistor;a 10th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, and the gate and the second source/drain are coupled to the second source/drain of the 8th transistor; anda 11th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a first bias, the first source/drain is coupled to the first source/drain of the 7th transistor, and the second source/drain is coupled to the second power cord.

22. The buffer amplifier as claimed in claim 21, wherein the first type differential amplifier comprises: a 12th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate receives a second bias, and the first source/drain is coupled to the first power cord;a 13th transistor, having a gate, a first source/drain, and a second source/drain, wherein the first source/drain is coupled to the first power cord, and the gate is coupled to the gate of the 9th transistor;a P-type differential pair, comprising: a 14th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the positive input terminal of the second type differential amplifier, and the first source/drain are coupled to the second source/drain of the 12th transistor; anda 15th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is the negative input terminal of the second type differential amplifier, the first source/drain is coupled to the second source/drain of the 12th transistor, and the second source/drain is coupled to the output terminal of the second type differential amplifier; anda 16th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate and the second source/drain are coupled to the second source/drain of the 14th transistor, and the first source/drain is coupled to the second power cord;a 17th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate and the second source/drain are coupled to the second source/drain of the 15th transistor, and the first source/drain is coupled to the second power cord; andan 18th transistor, having a gate, a first source/drain, and a second source/drain, wherein the gate is coupled to the gate of the 16th transistor, the first source/drain is coupled to the second power cord, and the second source/drain is coupled to the second source/drain of the 8th transistor.

23. The buffer amplifier as claimed in claim 22, wherein the 7th, 8th, 11th, 16th, 17th, and the 18th transistors are NMOSFETs, and the 9th, 10th, 12th, 13th, 14th, and the 15th transistors are PMOSFETs.

24. The buffer amplifier as claimed in claim 17, further comprising a capacitor having one terminal coupled to the second source/drain of the 5th transistor and another terminal coupled to the second source/drain of the 2nd transistor.