Buffer circuit and buffer control method

Abstract

A buffer circuit includes a storage unit having a first storage capacity that stores data based on a write request inputted from an outside and outputs the data in an order in which the data was written, based on a read request inputted from the outside. And a second storage capacity in the first storage capacity which is used to store the data is adjusted based on an amount of valid data which has been written into the storage unit but has not been read from the storage unit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above exemplary purpose, feature and advantage of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram showing a structural example of a buffer circuit according to a first exemplary embodiment of the present invention;

FIG. 2 is a block diagram showing a structural example of a write control unit in the first exemplary embodiment of the present invention;

FIG. 3 is a block diagram showing a structural example of a read control unit in the first exemplary embodiment of the present invention;

FIG. 4 is a block diagram showing a structural example of a data storage unit in the first exemplary embodiment of the present invention;

FIG. 5 is a block diagram showing a structural example of a buffer control unit in the first exemplary embodiment of the present invention;

FIG. 6 is a block diagram showing a detailed structural example of the buffer control unit in the first exemplary embodiment of the present invention;

FIG. 7 is a timing diagram showing an operation of the buffer circuit according to the first exemplary embodiment of the present invention in a state in which a value of a valid data amount counter is small;

FIG. 8 is a timing diagram showing an operation of the buffer circuit according to the first exemplary embodiment of the present invention in a state in which the value of the valid data amount counter increases;

FIG. 9 is a timing diagram showing an operation of the buffer circuit according to the first exemplary embodiment of the present invention in a state in which the increased value of the valid data amount counter decreases;

FIG. 10 is a block diagram showing a structural example of a buffer control unit in a second exemplary embodiment of the present invention;

FIG. 11 is a block diagram showing a detailed structural example of the buffer control unit in the second exemplary embodiment of the present invention;

FIG. 12 is a timing diagram showing an operation of a FIFO buffer circuit using the buffer control unit in the second exemplary embodiment of the present invention;

FIG. 13 is a block diagram showing a structural example of a conventional FIFO buffer circuit;

FIG. 14 is a block diagram showing a structural example of a write control unit in the conventional FIFO buffer circuit;

FIG. 15 is a block diagram showing a structural example of a read control unit in the conventional FIFO buffer circuit;

FIG. 16 is a block diagram showing a structural example of a data storage unit in the conventional FIFO buffer circuit; and

FIG. 17 a timing diagram showing an operation of a conventional FIFO buffer circuit.

Claims

1. A buffer circuit, comprising: a storage unit having a first storage capacity that stores data based on a write request inputted from an outside and outputs the data in a order in which the data was written, based on a read request inputted from the outside,wherein a second storage capacity in the first storage capacity which is used to store the data is adjusted based on an amount of valid data which has been written into the storage unit but has not been read therefrom.

2. A buffer circuit according to claim 1, wherein the storage unit comprises a plurality of buffer units whose total storage capacity is the first storage capacity andwherein the second storage capacity is determined by the number of used buffer units of the plurality of buffer units which number is changed corresponding to the amount of valid data.

3. A buffer circuit according to claim 2, further comprising, a valid data counting unit counting a word count of the valid data based on the number of input of the write request and the number of input of the read request,wherein the number of used buffer units is determined base on the word count.

4. A buffer circuit according to claim 3, wherein the number of used buffer units is determined based on a result obtained by comparison between the word count and a first value.

5. A buffer circuit according to claim 4, wherein when the word count is equal to the first value, the number of used buffer units increases andwhen the word count is smaller than the first value, the number of used buffer unit decreases.

6. A buffer circuit according to claim 2, wherein an operation of a buffer unit other than the used buffer units of the plurality of buffer units is stopped.

7. A buffer circuit according to claim 2, wherein supply of a clock to a buffer unit other than the used buffer units of the plurality of buffer units is stopped.

8. A buffer circuit according to claim 1, further comprising: a write pointer generating unit generating a write pointer which indicates a destination address of the data to be written into the storage unit and is incremented after the data is written;a read pointer generating unit generating a read pointer which indicates a source address of the data to be read from the storage unit and is incremented after the data is read; anda valid data counting unit for counting a word count of the valid data based on the number of input of the write request and the number of input of the read request,wherein the storage unit comprises a plurality of buffer units whose total storage capacity is the first storage capacity,wherein the number of a first buffer unit of the plurality of buffer units into which first buffer unit the data is written is determined base on the word count,wherein the write pointer comprises a write buffer specifying portion for specifying the first buffer unit into which the data is written, andwherein the read pointer comprises a read buffer specifying portion for specifying a second buffer unit of the plurality of buffer units from which second buffer unit the data is read.

9. A buffer circuit according to claim 8, wherein the number of the first buffer unit is determined based on a result obtained by comparison between the word count and a first value.

10. A buffer circuit according to claim 9, wherein when the word count is equal to the first value, the number of used buffer units increases andwhen the word count is smaller than the first value, the number of used buffer unit decreases.

11. A buffer circuit according to claim 9, further comprising, a buffer switch pointer holding unit for holding a value of the write pointer when the word count is equal to the first value,wherein, when a value held by the buffer switch pointer is equal to a value of the write pointer, the value of the write buffer specifying portion is changed to the value specifying the buffer unit into which the valid data is written, andwherein, when the value held by the buffer switch pointer is equal to a value of the read pointer, the value of the read buffer specifying portion is changed to a value specifying a buffer unit from which the valid data is read.

12. A buffer circuit according to claim 8, wherein the plurality of buffer units comprise a first buffer unit which can be continuously operated and a second buffer unit which can be operated only when the valid data retains.

13. A buffer circuit according to claim 8, wherein the plurality of buffer units comprise a first buffer unit to which a clock is continuously supplied and a second buffer unit to which a clock is supplied only when the valid data retains.

14. An electric device, comprising a buffer circuit according to claim 1.

15. A method of controlling a buffer circuit, comprising the steps of: writing data into a storage unit having a first storage capacity, based on a write request from an outside;reading the data from the storage unit in a order in which the data was written, based on a read request from an outside; andadjusting a second storage capacity in the first storage capacity which is used to write the data, based on an amount of valid data which has been written into the buffer unit but has not been read therefrom.

16. A method of controlling a buffer circuit according to claim 15, wherein the storage unit comprises a plurality of buffer units whose total storage capacity is the first storage capacity andwherein the second storage capacity is determined by the number of used buffer units of the plurality of buffer units which number is changed corresponding to the amount of valid data.

17. A method of controlling a buffer circuit according to claim 16, further comprising the steps of: counting a word count of the valid data based on the number of input of the write request and the number of input of the read request,wherein the number of used buffer units is determined base on the word count.

18. A method of controlling a buffer circuit according to claim 17, wherein the number of used buffer units is determined based on a result obtained by comparison between the word count and a first value.

19. A method of controlling a buffer circuit according to claim 16, further comprising the steps of: stopping an operation of a first buffer unit of the plurality of buffer units other than a second buffer unit of the plurality of buffer units in which the valid data remains; andstarting the operation of the first buffer unit when the second buffer unit is full with the valid data.