Buffer circuit using a transconductance multiplier

Abstract

The buffer circuit using a transconductance amplifier has a unity-gain feedback configured amplifier which includes: a first transistor M3; a second transistor M4 mirroring a current in the first transistor M3, the second transistor M4 is sized larger than the first transistor M3; a third transistor M1 coupled :o the first transistor; a fourth transistor M2 coupled to the second transistor M1, the fourth transistor M2 is sized larger than the third transistor M1; and a tail current source MS coupled to the third and fourth transistors M1 and M2. The second and fourth transistors M4 and M2 are sized larger than the first and third transistors M3 and M1 to form a transconductance multiplier. This reduces output impedance without increasing bias current.

Description

FIELD OF THE INVENTION

[0001] This invention generally relates to electronic systems and in particular it relates to buffer circuits using transconductance multipliers.

BACKGROUND OF THE INVENTION

[0002] The most commonly used buffers in CMOS integrated circuits are source followers, which are the simplest and potentially the fastest due to the single pole characteristic. However, the source follower also introduces level shifting which in some applications is undesired. When level shifting is a problem, unity-gain feedback configured amplifiers are typically used. But the output impedance of the unity-gain amplifier (buffer) is not as low as the source follower for a fixed bias current and the same transistor size.

[0003] The output impedance of the source followers is directly calculated as: 1$\begin{array}{cc}{r}_o\approx \frac{1}{g_m}=\frac{1}{\sqrt{k\frac{W}{L}{I}_D}}& \left(1\right)\end{array}$

[0004] where ID is the bias current of the MOS transistor and 2$\frac{W}{L}$

[0005] is the size of the transistor.

[0006] An example five-transistor unity gain amplifier is shown in FIG. 1. The amplifier includes transistors M1-M5, input VIN, output VOUT, source voltage VDD, and bias voltage VBIAS. For the unity-gain amplifier shown in FIG. 1, the output impedance can be easily calculated using the small signal model shown in FIG. 2. The small signal model includes current sources gm1*V1, gm2*V2, gm3*V3, and gm4*V3; resistors Ro1, Ro2, Ro3, Ro4, and Ro5; and voltages V1, V2, V3, Vx, and Vo; and current io. The output impedance calculation for the five-transistor unity gain amplifier is shown below:

g m2 (vo−vx)+gm4v3+(vo−vx)go2+vogo4=i o   (2)

v x g o5 +g m1 v x =g m2 (vo−vx)+(v3−vx)go1+(vo−vx)go2   (3)

g m1 v x −(v3−vx)go1−v3go3=gm3v3   (4)

[0007] Where go1-go5 are the transconductances for resistors Ro1-Ro5.

[0008] If the amplifier is biased properly, as usual, assume go<<gm and the mathematical derivations can be simplified. From equation (4), 3$v_3=\frac{g_{\mathrm{m1}}}{g_{\mathrm{m3}}}{v}_X,$

[0009] and from equation (3), 4$v_X=\frac{g_{\mathrm{m2}}}{g_{\mathrm{m1}}+g_{\mathrm{m2}}}{v}_O.$

[0010] Then from equation (2), substitute v3 and vx to get the output impedance ro as: 5$\begin{array}{cc}{r}_O=\frac{v_O}{i_O}=\frac{\left(g_{\mathrm{m1}}+g_{\mathrm{m2}}\right)g_{\mathrm{m3}}}{\left(g_{\mathrm{m3}}+g_{\mathrm{m4}}\right)g_{\mathrm{m1}}{g}_{\mathrm{m2}}}& \left(5\right)\end{array}$

[0011] Usually, the amplifier is designed symmetric where transistor M1 and M2 are equal, and transistor M3 and M4 are equal, and their bias currents are the same, thus gm1=gm2 and Gm3=gm4, so equation (5) can be further simplified as: 6$\begin{array}{cc}{r}_O=\frac{1}{g_{\mathrm{m1}}}=\frac{1}{\sqrt{k\frac{W}{L}{I}_{\mathrm{D1}}}}=\frac{1}{\sqrt{k\frac{W}{L}\frac{I_{\mathrm{TAIL}}}{2}}}& \left(6\right)\end{array}$

[0012] where 7$\frac{W}{L}$

[0013] is the size of the input pair M1 and M2.

[0014] Compared to equation (1), the output impedance of the unity-gain amplifier is {square root}{square root over (2)} times of that of a source follower with the same bias current and transistor size. To compensate the lost gm1, one has to either double the W or the bias current. But there is a point that increasing W will no longer lift gm1, then to increase the bias current is the only option.

SUMMARY OF THE INVENTION

[0015] A buffer circuit using a transconductance amplifier has a unity-gain feedback configured amplifier which includes: a first transistor; a second transistor mirroring a current in the first transistor, the second transistor is sized larger than the first transistor; a third transistor coupled to the first transistor; a fourth transistor coupled to the second transistor, the fourth transistor is sized larger than the third transistor; and a tail current source coupled to the third and fourth transistors. The second and fourth transistors are sized larger than the first and third transistors to form a transconductance multiplier. This reduces output impedance without increasing bias current.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the drawings

[0017] FIG. 1 is a schematic circuit diagram of a five-transistor unity gain amplifier;

[0018] FIG. 2 is a schematic circuit diagram o: a small signal model of the circuit of FIG. 1;

[0019] FIG. 3 is a detailed schematic circuit diagram of an example implementation of a preferred embodiment buffer circuit with a transconductance multiplier.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0020] In the preferred embodiment configuration, transistors M2 and M4, of FIG. 1, are sized larger than transistors M1 and M3. This reduces output impedance without increasing bias current or the transistor size by using a transconductance (Gm) multiplier. Looking at equation (5), assume gm4=x·gm3 and gm2=x·gm1, then the output impedance is 8$\begin{array}{cc}{r}_O=\frac{v_O}{i_O}=\frac{\left(1+x\right)g_{\mathrm{m1}}{g}_{\mathrm{m3}}}{\left(1+x\right)g_{\mathrm{m3}}{g}_{\mathrm{m1}}·x{g}_{\mathrm{m1}}}=\frac{1}{x·g_{\mathrm{m1}}}& \left(7\right)\end{array}$

[0021] which is x times smaller than in equation (6). In circuit design, the ratio x is simply obtained by sizing transistor M2 to x times transistor M1, and transistor M4 to x times transistor M3. Keep in mind that the above statement is only true transistor M1 size remains the same, which implies the transistor M2 and the total area will be roughly x times larger than the conventional unity-gain amplifier.

[0022] To make an accurate comparison with the conventional amplifier (x=1), assume the bias current ITAIL is fixed and e total transistor area remains the same. As shown in equation (6), for a conventional unity-gain amplifier, the output impedance ro is 9$\frac{1}{g_{\mathrm{m1}}}=\frac{1}{\sqrt{k\frac{W}{L}\frac{I_{\mathrm{TAIL}}}{2}}}.$

[0023] While for a Gm multiplied buffer, the output impedance ro is 10$\frac{1}{x·g_{\mathrm{m1}}}=\frac{1}{x\sqrt{k\left(\frac{W}{L}·\frac{2}{1+x}\right)\frac{I_{\mathrm{TAIL}}}{1+x}}}=\frac{1}{\frac{x}{1+x}\sqrt{k\frac{W}{L}\left(2·I_{\mathrm{TAIL}}\right)}}\approx \frac{1}{2\sqrt{k\frac{W}{L}\frac{I_{\mathrm{TAIL}}}{2}}},$

[0024] for the ratio x much greater than 1, and ro about 50% smaller than that of a conventional unity-gain amplifier. Even if x is not much greater than 1, ro is still 11$\frac{1+x}{2·x}$

[0025] of that of the conventional buffer. As a benefit, the bandwidth of the exact same circuit will be increased up to twice as wide.

[0026] The circuit of FIG. 3 is a buffer circuit example using the preferred embodiment Gm multiplier with x=9. The circuit of FIG. 3 includes NMOS transistors MN1-MN9; PMOS transistors MP1-MP7; inverter 20; bias current IBIAS; source voltages AVDD and AVSS; enable signals EN and ENB; input signals INP and INM; and output VOUT. In comparison with a conventional buffer with balanced input pair (x=1), the bandwidth of the preferred embodiment buffer is almost doubled. The internal parasitic pole also comes in at lower frequency due to smaller transconductance gm3.

[0027] While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. A circuit comprising: a first transistor; a second transistor mirroring a current in the first transistor, the second transistor is at least a few times larger than the first transistor; a third transistor coupled to the first transistor; a fourth transistor coupled to the second transistor, the fourth transistor is at least a few times larger than the third transistor; and a tail current source coupled to the third and fourth transistors.

2. The circuit of claim 1 wherein the first, second, third, and fourth transistors are MOS transistors.

3. The circuit of claim 1 wherein the first and second transistors are PMOS transistors.

4. The circuit of claim 1 wherein the third and fourth transistors are NMOS transistors.

5. The circuit of claim 1 further comprising a fifth transistor coupled between the second and fourth transistor.

6. The circuit of claim 5 wherein the fifth transistor is a PMOS transistor.

7. The circuit of claim 1 wherein a gate of the third transistor is coupled to a first input node and a gate of the fourth transistor is coupled to a second input node.

8. The circuit of claim 1 wherein an output node is coupled between the second transistor and the fourth transistor.

9. A buffer circuit comprising: a first MOS transistor having a gate coupled to a first input node; a second MOS transistor coupled to the first MOS transistor; a third MOS transistor having a gate coupled to a gate of the second MOS transistor, the third MOS transistor is at least a few times larger than the second MOS transistor; a fourth MOS transistor coupled to the third MOS transistor and having a gate coupled to a second input node, the fourth MOS transistor is at least a few times larger than the first MOS transistor; and a tail current source coupled to the first and fourth transistors.

10. The circuit of claim 9 wherein the second and third MOS transistors are PMOS transistors.

11. The circuit of claim 9 wherein the first and fourth MOS transistors are NMOS transistors.

12. The circuit of claim 9 further comprising a fifth MOS transistor coupled between the second and fourth transistor.

13. The circuit of claim 12 wherein the fifth MOS transistor is a PMOS transistor.

14. The circuit of claim 9 wherein an output node is coupled between the third MOS transistor and the fourth MOS transistor.

15. The circuit of claim 9 wherein the gate of the second MOS transistor is coupled to a drain of the second MOS transistor.