Claims
- 1. Buffer circuit for a load (LAS) to be supplied directly by a supplied DC voltage (Uv), with a buffer capacitor (Cp), which may be charged to a voltage (UH) by means of a charging circuit (HSS), which voltage is higher than the supply voltage, and which can be brought in to supply the load in the event of dips in the supply voltage via a discharging circuit (TSS), characterized by a step-down controller (TSS), whose input is coupled to the buffer capacitor (Cp) and whose output is coupled to the load (LAS) and to the supply DC voltage (Uv), and a trigger circuit (TRI), which is configured to activate the step-down controller in the event of dropout of the supply voltage at the load.
- 2. Buffer circuit according to claim 1, characterized in that the charging circuit is a step-up controller (HSS), whose input is coupled to the load (LAS) and use output is coupled to the buffer capacitor (Cp).
- 3. Buffer circuit according to claim 1 or 2, characterized in that the trigger circuit (TRI) is configured to deliver switching pulses to the step-down controller (TSS).
- 4. Buffer circuit according to claim 1, characterized in that a potential segregation means (T2) is provided for the trigger circuit (TRI).
- 5. Buffer circuit according to claim 4, characterized in that the potential segregation means is a transformer (T2), via which the output of the trigger circuit (TRI) is connected to the step-down controller (TSS).
- 6. Buffer circuit according to claim 2, characterized in that the step-up controller (HSS) has a first controlled switch (V1), via which a first inductance (L1) can be periodically connected to the load voltage (Uv), plus a first capacitor (C1) coupled in parallel to the load, as well as a first diode (D1) leading to the buffer capacitor (Cp) from the connection of the first inductance with the first switch.
- 7. Buffer circuit according to claim 1, characterized in that the step-down controller (TSS) has a second controlled switch (V2), via which the voltage (UH) on the buffer capacitor (Cp) can be periodically connected to the load (LAS) in series with a second inductance (L2), to which load a second capacitor (C2) is coupled in parallel, and the series connection of the second inductance with the second capacitor is jumpered by a backflow diode (D2).
Priority Claims (1)
Number |
Date |
Country |
Kind |
966/2000 |
May 2000 |
AT |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application is a National Phase Patent Application of International Application Number PCT/AT01/00176, filed on May 30, 2001, which claims priority of Austrian Patent Application Number A 966/2000, filed May 31, 2000
PCT Information
Filing Document |
Filing Date |
Country |
Kind |
PCT/AT01/00176 |
|
WO |
00 |
Publishing Document |
Publishing Date |
Country |
Kind |
WO01/93411 |
12/6/2001 |
WO |
A |
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4197582 |
Johnston et al. |
Apr 1980 |
A |
5714863 |
Hwang et al. |
Feb 1998 |
A |
6366070 |
Cooke et al. |
Apr 2002 |
B1 |
Foreign Referenced Citations (5)
Number |
Date |
Country |
38 05 256 |
Aug 1989 |
DE |
195 42 085 |
Jul 1996 |
DE |
0 798 840 |
Oct 1997 |
EP |
0 798 840 |
Oct 1997 |
EP |
0 798 840 |
Oct 1997 |
EP |
Non-Patent Literature Citations (2)
Entry |
International Search Report of PCT/AT01/00176, dated Oct. 11, 2001. |
International Preliminary Examination Report of PCT/AT01/00176, dated Apr. 9, 2002. |