Claims
- 1. In a data storage device having a controller and a read/write channel integrated on a semiconductor substrate, a method of functionally testing the controller comprising steps of:
providing a Non-Return to Zero (NRZ) data bus on the substrate between the controller and the read/write channel; providing a test first-in/first-out buffer (FIFO) between a microprocessor and the controller via the NRZ data bus; sending a burst of data through the FIFO via the NRZ data bus to the controller; and monitoring the data received by the controller.
- 2. The method of claim 1 further comprising a step of checking data received by the controller to the data sent through the FIFO.
- 3. The method of claim 2 wherein the step of monitoring comprises monitoring controller status registers and ECC status registers.
- 4. The method of claim 1 wherein the sending step comprises sending user data from the microprocessor through the FIFO buffer.
- 5. The method of claim 1 wherein the data storage device is a disc drive.
- 6. The method of claim 5 further comprising a step of checking data received by the controller to the data sent through the FIFO.
- 7. The method of claim 6 wherein the step of monitoring comprises monitoring controller status registers and ECC status registers.
- 8. The method of claim 5 wherein the sending step comprises sending user data from the microprocessor through the FIFO buffer.
- 9. In a data storage device having a controller and a read/write channel integrated on a semiconductor substrate, a method of functionally testing the controller comprising steps of:
providing a Non-Return to Zero (NRZ) data bus on the substrate between the controller and the read/write channel; providing a test first-in/first-out buffer (FIFO) operably connected to the NRZ data bus; writing a burst of user data through the controller to the NRZ data bus to the test FIFO; and monitoring the user data received by the test FIFO from the NRZ data bus.
- 10. The method of claim 9 wherein the data storage device is a disc drive.
- 11. The method according to claim 9 wherein the monitoring step comprises comparing the burst of user data to data received by the test FIFO.
- 12. The method according to claim 11 further comprising a step of comparing controller and ECC status registers to determine whether the burst of user data sent matches the user data received by the test FIFO buffer.
- 13. The method according to claim 10 wherein the monitoring step comprises comparing the burst of user data to data received by the test FIFO.
- 14. The method according to claim 13 further comprising a step of comparing controller and ECC status registers to determine whether the burst of user data sent matches the user data received by the test FIFO.
- 15. The method of claim 14 wherein written data is verified by reading content of the FIFO after each burst.
- 16. A data storage device comprising:
a controller and read/write channel integrated on a semiconductor substrate; a Non-Return to Zero (NRZ) data bus connecting the controller with the read/write channel; and means on the semiconductor substrate for functional testing of the controller.
- 17. The device according to claim 16 wherein the means for testing comprises:
a test first in/first out buffer (FIFO) and control logic module on the substrate operably connected to the NRZ data bus.
- 18. The device according to claim 17 wherein the module comprises:
a test FIFO connectable to the NRZ data bus; a programmable clock operable to provide a reference clock signal to the controller; a control register connected to the FIFO and providing a clock select to a multiplexer connected to the programmable clock; and a counter connected to the reference clock signal operable to stop the reference clock signal to the controller when a predetermined count is reached.
- 19. The device according to claim 18 wherein the FIFO is connected to a microprocessor
- 20. The device according to claim 18 wherein the module includes a control register operable to enable the NRZ test FIFO connection to the NRZ data bus and provide a clock select signal to the multiplexer.
- 21. An integrated circuit apparatus for a data storage device comprising:
a semiconductor substrate; a controller and a read/write channel formed on the substrate; a non-return to zero data bus on the substrate connecting the controller to the read/write channel; and a test non-return to zero first in/first out buffer (FIFO) formed on the substrate connectable to the NRZ data bus between the controller and the read/write channel in a test mode of operation.
- 22. The apparatus of claim 21 further comprising a programmable clock on the substrate operable to provide a reference clock signal to the controller in the test mode of operation.
- 23. The apparatus of claim 22 further comprising a multiplexer on the substrate connected to the clock and receiving a clock select signal from a control register connected to the FIFO.
- 24. The apparatus of claim 22 further comprising a counter receiving the reference clock signal operable to block the reference clock signal to the controller upon a predetermined count.
RELATED APPLICATIONS
[0001] This application claims priority of U.S. provisional application Serial No. 60/355,670, filed Feb. 5, 2002.
Provisional Applications (1)
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Number |
Date |
Country |
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60355670 |
Feb 2002 |
US |