Patent Application
20170060153
Electronic system designers needing voltage regulation often employ low-dropout (“LDO”) regulators, as these regulators offer a desirable combination of features. For example, LDO regulators can offer high-performance regulation over a wide range of load currents even when the supply voltage is very close to the output voltage. As they are linear voltage regulators, they do not require rapid switching and hence they produce no switching noise. Their relatively simple architecture requires no inductors or transformers, enabling them to be implemented with a relatively small device size. Nevertheless, an even smaller size would be desirable, so long as it can be achieved without sacrificing regulator performance or efficiency.
Accordingly, there is disclosed herein a bulk-current regulation technique for improving output transistor performance, which in the context of an LDO regulator, reduces dropout without requiring a larger transistor and without sacrificing efficiency by, e.g., reducing threshold voltage and thereby increasing leakage current. An illustrative method embodiment includes: sensing a source-drain current provided by the output transistor; and controlling a bulk current from a body terminal of the output transistor in response to the source-drain current. The controlling includes: maintaining the bulk current at an operating value while the source-drain current is in an active range; and reducing the bulk current below the operating value when the source-drain current lies outside the active range.
An illustrative circuit embodiment includes: an output transistor that supplies an output current over a range that includes an active region; and a bulk current adapter that senses the output current and responsively controls a bulk current from a body terminal of the output transistor, maintaining the bulk current at an operating value while the output current is in the active region and reducing the bulk current when the output current is outside the active region. The illustrative circuit may be implemented as part of a low dropout (LDO) regulator.
In the drawings:
It should be understood that the drawings and corresponding detailed description do not limit the disclosure, but on the contrary, they provide the foundation for understanding all modifications, equivalents, and alternatives falling within the scope of the appended claims.
The output transistor(s) of devices such as LDO regulators are often required to supply significant currents with a minimal voltage drop. The device specifications may accordingly require that the transistor size be undesirably large and/or be provided with an undesirably low threshold current. To relax these limits, the present disclosure modifies the bulk current of the device, preferably in an adaptive fashion that preserves the device's efficiency at low output currents.
To provide an illustrative context,
The application schematic shows a power supply Vsupply coupled between the ground and the supply voltage pin Vc. A voltage reference is also coupled between the ground and the supply voltage to supply a reference voltage signal to the input pin IN. A current source is coupled to the Ibias pin. On the output side, an output capacitor Cout is coupled between ground and the output pin OUT, and a (variable) load resistance Rload is coupled in parallel with the output capacitor Cout. Two resistors R1, R2 are coupled in series between ground and the output pin OUT to form a voltage divider. The intermediate node of the voltage divider is coupled to the feedback pin FB.
With this figure as context, we turn to
MOS transistors are fundamentally four-terminal devices, having a source terminal, a drain terminal, a gate terminal, and a body terminal. Though the body terminal is normally shorted to the source terminal, it need not be. Rather, the body terminal can be driven separately to modify the transistor's threshold voltage. In the regulator of
To regulate the bulk current Ibulk (and thereby control the voltage of the bulk node and body terminal of the output transistor), the regulator of
In the embodiment of
Conversely, a decrease in the input voltage increases the conductivity of the sense and output transistors, increasing the current provided to the output pin. The gate voltage of the leakage transistor is increased, lowering the bulk node voltage and further enhancing the conductivity of the output transistor, enabling the voltage drop across the output transistor to be minimized under conditions where high output currents are desired.
Note that the illustrated series arrangement of the bulk current adapter block is but one implementation. Any suitable arrangement that adjusts the bulk current based on the drain current of the sense transistor Ms (or indeed, on the drain current of the output transitor Mout) may alternatively be employed.
Transistor M7, along with transistors M6 and M3, are configured as current mirrors of bias current transistor M2, coupled between the current bias pin and ground. The gates of transistors M3, M6, and M7 are each coupled to the drain of transistor M2. Transistors M2, M3, M6, M7 and Mleak are each NMOS transistors.
Transistor M6 draws the bias current through a PMOS bias current transistor M13. PMOS transistors M14 and M15 are configured as current mirrors of transistor M13, and the gates of PMOS transistors M16, M17 are biased between bias transistors M6 and M13. With the biasing provided by transistors M3, M14, and M15, NMOS transistors M0 and M1 act as a differential amplifier. The gate of transistor M0 is coupled to the input pin IN, and the gate of transistor M1 is coupled to the feedback pin FB. As the feedback voltage rises beyond the input pin voltage, M1's drain voltage drops, reducing the current flow through transistor M17, which in turn reduces the conductivity of transistor M4 and its current mirror M9. M0's drain voltage increases, increasing the current flow through transistors M16 and M9. The output transistor's gate is coupled to the drain of transistor M9, so the gate voltage rises, reducing the current flow to the output pin. Conversely, as the feedback pin voltage falls below the input pin voltage, the output transistor's gate voltage falls, increasing the current flow to the output pin.
The regulator of
It is desirable to minimize the device's quiescent current Iq (the ground current when the output current is zero) and to minimize the maximum dropout (the voltage drop across the output transistor at the maximum rated output current). For a given input voltage and supply voltage, the gate voltage of the output transistor corresponds (inversely) to the output current. To reduce quiescent current without increasing the maximum dropout, the bulk current is related to the output current via the sense transistor Ms and the bulk current adapter block.
When the disclosed bulk current regulation technique is applied to existing designs, it is expected that significantly lower LDO dropouts will be achieved. The disclosed techniques may also be employed as a way to significantly reduce die area while maintaining an LDO dropout, or as a way to reduce both die area and LDO dropout. Though described above for use with a PMOS output transistor, the disclosed technique is also applicable to NMOS output transistors, or with any suitable integrated field effect transistor.
In a simulation trial using an LDO regulator fabricated with a 5.5V process, maximum dropout was set to 190 mV. With Vout=1.45V and the operating value of Ibulk set to 3 uA, the areal requirement for the output transistor was reduced by 40% for the same dropout. If, for example, the output transistor occupied 50% of the total die area, this technique enables the total die area to be reduced by 20%. With Ibulk kept at 3 uA, at Vout=2.2V the output transistor size reduction was 23%, and at Vout=3V, the reduction was 15%. To illustrate how the Ibulk influences dropout, we note the 190 mV dropout for the original design (at Vout=1.45V) required Ibulk=1 uA. Increasing Ibulk to 27 uA reduced the dropout to 174 mV.
Though the disclosed technique is discussed in the particular context of LDO regulators, it is applicable to other integrated circuit devices. These and numerous other modifications, equivalents, and alternatives, will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such modifications, equivalents, and alternatives where applicable.
