Patent Application
20230006424
The technical field generally relates to photonic devices and related systems, as well as methods for manufacturing the same. More particularly, the technical field relates to buried heterostructure semiconductor optical amplifiers and related systems, and methods for fabricating the same.
An optical amplifier is a device that receives an input signal and generates an output signal having a higher power than the input signal.
Existing types of optical amplifiers include but are not limited to erbium-doped fiber amplifier (EDFA), Raman amplifier (ROA) and semiconductor optical amplifier (SOA). These optical amplifiers are all associated with respective challenges. For example, the EDFA is not only expensive to manufacture, but it is also bulky, because it requires a pump source, a coupler and an isolator. The ROA is associated with similar challenges but is even more expensive to produce than the EDFA. The SOA is typically more compact than the EDFA and ROA, can be more easily monolithically integrated with other devices and is also generally cheaper to produce. However, the noise figure is generally better in EDFA and ROA than in SOA.
Buried heterostructure SOA (BHet SOA) is a subclass of optical amplifiers. The fabrication of a BHet SOA has been commonly carried out along the <011> direction of the substrate (sometimes referred to as the “conventional direction”). One method for manufacturing a BHet SOA relies on three epitaxial growth steps, such as metalorganic chemical vapour deposition (MOCVD) growth steps, resulting in a complex and lengthy process.
There is thus a need for techniques, methods, systems and devices that addresses or mitigate at least some of the challenges presented above.
In accordance with one aspect, there is provided a method for fabricating a buried heterostructure semiconductor optical amplifier, comprising:
In some embodiments, the dielectric layer is a silicon oxide.
In some embodiments, the substrate is an n-type substrate.
In some embodiments, the n-type substrate is InP.
In some embodiments, the method further comprises cleaning the substrate before coating the substrate with the dielectric layer.
In some embodiments, said defining the openings in the dielectric layer comprises defining narrow openings in the dielectric layer and defining large openings.
In some embodiments, each narrow opening has a width ranging from about 2 μm to about 5 μm and each large opening has a width ranging from about 50 μm to about 250 μm.
In some embodiments, the dielectric layer has a thickness ranging from about 1000 Å to about 15000 Å.
In some embodiments, defining the openings in the dielectric layer comprises orienting the openings with an angle ranging from about 0° to about 10° with a <0-11> direction of the substrate.
In some embodiments, the angle is about 0°.
In some embodiments, the angle is about 7°.
In some embodiments, said etching, in situ, the uncovered regions of the substrate is carried out using a shallow etch.
In some embodiments, said shallow etch comprises etching the substrate for 1000 Å to about 15000 Å.
In some embodiments, said etching, in situ, the uncovered regions of the substrate comprises using a precursor selected from methyl iodide, carbon tetrabromide, carbon chloride tetrabromide, carbon bromide trichloride and carbon tetrachloride.
In some embodiments, said diffusing, in situ, the portion of the p-dopant in the substrate includes diffusing Zn.
In some embodiments, the distribution profile has a vertical diffusion depth ranging from about 0.4 μm to about 1.0 μm.
In some embodiments, said diffusing, in situ, the portion of the p-dopant in the substrate is carried out using a ratio of lateral diffusion rate to vertical diffusion rate in the range of about 0.5 to about 1.0.
In some embodiments, the tapered recess has a vertical dimension ranging from about 0.7 μm to about 1.7 μm.
In some embodiments, said growing the n-blocking layer in the tapered recess comprises growing an InP blocking layer.
In some embodiments, the n-blocking layer has a thickness ranging from about 0.5 μm to about 0.8 μm.
In some embodiments, said growing the active region comprises growing at least one quantum well.
In some embodiments, said growing the active region comprises growing a bulk material.
In some embodiments, said growing the active region comprises growing quantum dots.
In some embodiments, said growing the p-overclad over the active region comprises growing an InGaAs layer.
In some embodiments, the method further comprises doping the InGaAs with Zn.
In some embodiments, the method further comprises thinning the backside of the substrate before growing the n-metal contact thereon.
In accordance with another aspect, there is provided a method for fabricating a buried heterostructure semiconductor optical amplifier, comprising:
In accordance with another aspect, there is provided a buried heterostructure semiconductor optical amplifier, comprising:
In some implementations, there is provided a method combining selective area growth (SAG), in situ Zn-diffusion using MOCVD techniques and in situ etching techniques in a single MOCVD run to obtain a BHet SOA structure having a lateral npnp blocking layer.
In some implementations, there is provided a method for fabricating a BHet SOA oriented along an angle ranging from about 0° to about 10° with a <0-11> direction of the substrate. In some embodiments, the BHet SOA is monolithically integrated with an optical modulator. In some embodiments, the angle is about 7°.
Other features will be better understood upon reading of embodiments thereof with reference to the appended drawings.
In the following description, similar features in the drawings have been given similar reference numerals. In order to not unduly encumber the figures, some elements may not be indicated on some figures if they were already mentioned in preceding figures. It should also be understood herein that the elements of the drawings are not necessarily drawn to scale and that the emphasis is instead being placed upon clearly illustrating the elements and structures of the present embodiments.
The terms “a”, “an” and “one” are defined herein to mean “at least one”, that is, these terms do not exclude a plural number of elements, unless stated otherwise. It should also be noted that terms such as “substantially”, “generally” and “about”, that modify a value, condition or characteristic of a feature of an exemplary embodiment, should be understood to mean that the value, condition or characteristic is defined within tolerances that are acceptable for the proper operation of this exemplary embodiment for its intended application.
In the present description, the terms “connected”, “coupled”, and variants and derivatives thereof, refer to any connection or coupling, either direct or indirect, between two or more elements. The connection or coupling between the elements may be mechanical, physical, optical, acoustical, operational, electrical, wireless, or a combination thereof.
In the present description, the terms “light” and “optical”, and any variants and derivatives thereof, are intended to refer to electromagnetic radiation in any appropriate region of the electromagnetic spectrum and are not limited to visible light. For example, in one embodiment, the terms “light” and “optical” may encompass electromagnetic radiation in one or more regions of the electromagnetic spectrum, such as, for example and without being limitative, the millimeter, terahertz, visible and ultraviolet regions.
It will be appreciated that positional descriptors indicating the position or orientation of one element with respect to another element are used herein for ease and clarity of description and should, unless otherwise indicated, be taken in the context of the figures and should not be considered limiting. It will be understood that spatially relative terms (e.g., “away”, “vertical” and “horizontal”, “top” and “bottom”, “over”, “under”, “front” and “rear”, “behind”, “side” and the like) are intended to encompass different positions and orientations in use or operation of the present embodiments, in addition to the positions and orientations exemplified in the figures.
In the following description, the expression “quantum well” or “QW” generally refers to a heterostructure in which charged carriers of at least one type (i.e., electrons and/or holes) are confined in one direction (typically out-of-plane) and free in the other two directions (typically the in-plane directions). Quantum confinement is a quantum property that emerges when a particle is localized in a volume that has at least one reduced lateral dimension, e.g., a few nanometers. In this situation, the energy of the particle becomes quantized in this direction.
The expression “device” refers to a component or an assembly associated with a functionality. For example, an “photonic device” is a device that can accomplish a specific functionality involving the use or manipulation photons and/or charges carriers.
Techniques and methods for fabricating a BHet SOA using an integrated process are provided. Various embodiments of these techniques and methods will be described in greater detail after the following overview of some theoretical considerations.
General Theoretical Background
The fabrication of a BHet SOA oriented along the direction of <0-11> of the substrate may be desirable in cases where a monolithic integration of SOA with another optoelectronic component such as an optical modulator is sought.
However, methods for fabricating such a BHet SOA remain challenging, as it will be outlined below.
The fabrication of a BHet SOA along <0-11> direction may be achieved using a method relying on three epitaxial steps, such as MOCVD growth steps. In this method, a base epitaxial growth including a n-InP layer and an active region layer is carried out on an n-InP substrate. After forming a narrow mesa via an ex-situ etching, a blocking layer is grown via a SAG process. Then, a blanket p-type overclad is grown. Finally, a mesa is formed via an ex-situ etching, followed by a metallization step. In this method, the current confinement is achieved via npnp blocking layers that are formed as a result of the process. This method, relying on three MOCVD growth steps is complex and lengthy. In addition, the relatively poor quality of the npnp blocking layer overgrown along the <0-11> has hindered the success of this method.
An alternative method would be to employ a SAG technique to reduce the number of epitaxial steps during the fabrication of the SOA. An example of this approach is disclosed in U.S. Pat. No. 5,659,565. The teachings of this document relate to the fabrication of SOAs along the <011> direction, i.e., along the conventional direction, but being tilted by about 5° thereof. In this method, the active core is located adjacent to a thin SiOx dielectric mask and is surrounded by a p-type InP overclad. According to this method, the leakage of the current into the substrate is suppressed by the SiOx, dielectric mask. The method reported in this document is compatible with SOAs fabricated along the <011> direction only.
Buried Heterostructure Semiconductor Optical Amplifier
Techniques and methods to produce a BHet SOA are provided. In accordance with one broad aspect, there is provided a method that combines SAG, in situ MOCVD p-dopant, such as Zn, diffusion and in situ etching techniques in a single MOCVD run to manufacture a BHet SOA structure having lateral npnp blocking layers, as it will be described in greater detail below. In nearly all variants, the BHet SOA are based on III-V semiconductors.
The embodiments of the methods for fabricating a BHet SOA that will now be presented can be carried in a single continuous process, i.e., an in-situ process or integrated process, which can be, for example and without being limitative a single MOCVD process. The complexity associated with these embodiments is relatively low and comparable to the complexity of designing shallow ridge SOA. An example of a shallow ridge SOA from prior art is illustrated in
An exemplary embodiment of a BHet SOA 20 is shown in
Referring to
The method includes a step of coating the substrate 22 with a dielectric layer 24. A non-limitative example of the dielectric layer 24 is a silicon oxide (SiOx). The dielectric layer 24 can be provided on the substrate 22 using coating and deposition techniques that are already known in the art. The substrate 22 is an n-type substrate, such as, for example and without being limitative, InP. It is to be noted that, in some embodiments, the method includes one or more precleaning steps before coating the substrate 22. Such precleaning steps can be useful to remove contaminants from the external surface of the substrate 22.
The step of coating the substrate 22 is followed by a step 100 of defining openings 26 in the dielectric layer 24 to obtain uncovered regions of the substrate. Coating the substrate 22 with the dielectric layer 24 and defining the openings 26 therein to obtain the uncovered regions of the substrate 22 are made using common microfabrication techniques. For example, and without being limitative, the step 100 of defining the openings 26 in the dielectric layer 24 may include patterning a photoresist layer provided on top of the dielectric layer 24 and etching the same after its patterning. The dielectric layer 24 can be coated with a photoresist layer of positive photoresist or negative photoresist. A characteristic of the positive photoresist is that the portion of the positive photoresist that is exposed to light (e.g., through a photomask during an “exposition step”) becomes soluble to a photoresist developer (i.e., during a “developing step”). Upon exposition to light through the photomask, the photo-sensitive material forming the positive photoresist will be degraded by light and the photoresist developer will dissolve the portions exposed to light, whereas the blocked or unexposed portions of the photoresist remain insoluble to the photoresist developer. After exposition and development of the positive photoresist, the patterns provided therein are thus a copy of the mask. A characteristic of the negative photoresist is that the portion of the negative photoresist that is exposed to light (i.e., through the photomask during the “exposition step”) becomes insoluble to the photoresist developer (i.e., during the “developing step”). Upon exposition to light through the photomask, the photo-sensitive material forming the negative photoresist will be cross-linked or polymerized by light and the photoresist developer will dissolve the blocked portions or portions unexposed to light, whereas the exposed portions of the photoresist remain insoluble to the photoresist developer. After exposition and development of the negative photoresist, the patterns provided therein are thus complementary to the mask. The photoresist, positive or negative, can be spin-coated on the dielectric layer core or could alternatively be coated or deposited with other deposition techniques. In a typically spin-coating step, a few milliliters of the photoresist are placed, poured or dispensed on the dielectric layer. A rotational movement is then imparted to the substrate 22 having the dielectric layer 24 thereon and a rotational speed equal to or greater than 1000 rpm can be reached. The centrifugal force due to the rotation of the substrate 22 spreads the dispensed photoresist into a thin film of substantially uniform thickness and the excess is spun off the edge of the substrate 22 and dielectric layer 24. Part of the solvent contained in the photoresist can evaporate from the photoresist layer during the rotation of the substrate. The photoresist layer is then exposed to electromagnetic radiation through openings provided in a photomask placed above the photoresist layer. Of note, electron beam lithography could alternatively be used. As in most microfabrication process, the electromagnetic radiation is in the UV range. In some embodiments, exposing the photoresist layer to electromagnetic radiation comprises illuminating the photoresist layer with a beam having at least one ultraviolet spectral line. In some embodiments, the spectral line comprises 436 nm, 405 nm and 365 nm. After the exposition of the photoresist layer, the photoresist layer is developed in an appropriate solvent. In some embodiments, remaining portions of the photoresist layer after the development can be thermally treated in order to harden the same. In some embodiments, the remaining portions can be hardened using deep ultra-violet (DUV) radiation. Once the development of the photoresist is complete, a step of etching the exposed portions of the dielectric layer, which is followed by a step of stripping off the remaining portions of the photoresist layer, thus resulting in the dielectric layer having openings defined therein and portions of the substrate being uncovered, namely the uncovered regions. An example of the dielectric layer 24 coating the substrate 22 is illustrated in
In some embodiments, the thickness of the dielectric layer 24, which corresponds to the depth of the openings 26 provided therein, is in the range of about 1000 Å to about 15000 Å. As for the width (i.e., an opening size), it is typically in the range of about 2 μm to about 5 μm. Such openings 26 are referred to as “narrow openings”. It is to be noted that the dielectric layer 24 can also be provided with large openings to control the global growth rate during the SAG step(s). An example of the layout of the dielectric mask is illustrated in
Once the openings 26 are defined in the dielectric layer 24, a step 102 of etching, in situ, the uncovered regions of the substrate 22 to form angles 27 at corresponding edges thereof is carried out
The angles 27 are different than the relatively flat surface of the uncovered regions of the substrate 22. For example, and without being limitative, the angles 27 can supplementary, i.e., their sum can be 180°. In the context of the current description, the angles 27 are measured in a direction aligned with the width of the openings 26 (i.e., perpendicular to their longitudinal axis). This step 102 could be referred as a “shallow etch step”, as the depth of this etching is relatively small. Indeed, the aim of this in situ etching is to form the angles 27 at the edges of the openings 26 of the dielectric layer 24, rather than etching the substrate 22. In some embodiments, the depth of the shallow in situ etching is in the range of about 0.1 μm to about 0.5 μm. Non-limitative examples of precursors that can be used for this step 102 are methyl iodide, carbon tetrabromide, carbon chloride tetrabromide, carbon bromide trichloride, carbon tetrachloride and other precursors that are compatible with MOCVD technologies. An example of the result of this step 102 is illustrated in
With reference to
The step 102 of forming the angles 27 at the edges of the openings 26 is followed by a step 104 of diffusing, in situ, a p-dopant in the uncovered regions of the substrate to obtain a p-dopant distribution 28 in a portion of the substrate 22. This step 104 is illustrated in
Now referring to
The method then includes subsequent growth steps 108 to 114, as illustrated in the non-limitative embodiment of
A schematic representation of the obtained device is illustrated in
One advantage associated with the embodiments of the method described herein is that they result in devices having lateral current blocking layers, which is at least partially due to the methods relying on SAG, p-dopant (e.g., Zn) diffusion and in situ etching step(s) in a single MOCVD run.
In other embodiments, the methods provided herein can be adapted so that the active region or core is not buried into the substrate, but is rather above the substrate, i.e., protruding therefrom. In such embodiments, the active region is surrounded by the p-overclad material. An example of a device resulting from this process is illustrated in
Example of an Implementation
Now that several embodiments of techniques for fabricating BHet SOA have been presented, a nonlimitative exemplary implementation will now be presented.
An n-substrate, for example and without being limitative, an InP substrate or any other III-V substrate is covered with a dielectric layer such as SiOx. The thickness of SiOx is in the range of about 1000 Å to about 15000 Å. The substrate is then patterned to open two sets of windows. The first set of windows includes narrow openings, for the growth of the device structure, and has a width (i.e., an opening size) in the range of about 2 μm to about 5 μm. The second set of windows includes wide windows, for adjusting the overall growth rate, and has a width (i.e., an opening size) in the range of about 50 μm to about 250 μm. The separation between narrow and wide openings was in the range of about 25 μm to about 250 μm. The stripes were oriented with an angle θ in the range of about 0° to about 10° relative to the <0-11> direction.
The substrate is then loaded into a semiconductor growth tool, such as an MOCVD reactor after a preclean process. Prior to the Zn diffusion process, a shallow in situ etching is carried out using ethyl iodide. Alternatively, methyl iodide, carbon tetrabromide, carbon tetrachloride or carbon bromide trichloride could be used for the in situ etching step. The depth of the shallow in situ etching is in the range of about 0.1 μm to about 0.5 μm. The step of shallow etching is required to control the ratio of the lateral to vertical Zn diffusion rate of the subsequent step that will now be described.
The step of Zn diffusion is then carried out. The Zn diffusion depth is in the range of about 0.4 μm to about 1.0 μm. The ratio of lateral to vertical diffusion rate is in the range of about 0.5 to about 1.0, depending on the diffusion conditions and the shallow etching depth carried out in the prior step.
After the step of Zn diffusion, a step of in situ etching is carried out. The depth of the in situ etching is in the range of about 0.7 μm to about 1.7 μm.
After the step of in situ etching, an n-blocking layer, such as n-InP layer, with thickness in the range of about 0.5 μm to about 0.8 μm and n-doping level in the range of about 6e17 cm−3 to about 2e18 cm−3 is grown.
After this step of growing the n-blocking layer, an active region is grown. The active region could be in the form of a bulk material, multi-quantum wells or quantum dots.
As a final epitaxial step, a p-overclad layer, such as a p-InP layer, and a p-contact, such as InGaAs layer, are grown. The p-doping is achieved using Zn or any other appropriate dopants. The doping level of the overclad is in the range of about 5e17 cm−3 to about 2e18 cm−3, and the doping level of the contact layer is in the range of about 1e19 cm−3 to about 2e19 cm−3.
In order to complete the fabrication process, after depositing a dielectric layer and providing opening via over the contact layer in the device region, a p-metal contact is deposited on the contact layer. Finally, after thinning the wafer, an n-metal contact is deposited on the backside of the wafer.
In another implementation, there is provided an SOA structure wherein the active core is not buried into the substrate but is above the substrate and is surrounded by a p-overclad. An example of such a fabricated SOA structure is shown
Several alternative embodiments and examples have been described and illustrated herein. The embodiments described above are intended to be exemplary only. A person skilled in the art would appreciate the features of the individual embodiments, and the possible combinations and variations of the components. A person skilled in the art would further appreciate that any of the embodiments could be provided in any combination with the other embodiments disclosed herein. The present examples and embodiments, therefore, are to be considered in all respects as illustrative and not restrictive. Accordingly, while specific embodiments have been illustrated and described, numerous modifications come to mind without significantly departing from the scope defined in the appended claims.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CA2020/051707 | 12/11/2020 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 62946633 | Dec 2019 | US |
