This application is a continuation of U.S. patent application Ser. No. 08/457,651, filed Jun. 1, 1995, now U.S. Pat. No. 5,675,549.
Number | Name | Date | Kind |
---|---|---|---|
4344156 | Eaton et al. | Aug 1982 | |
4484308 | Lewandowski et al. | Nov 1984 | |
4562555 | Ouchi et al. | Dec 1985 | |
4567579 | Patel et al. | Jan 1986 | |
4575825 | Ozaki et al. | Mar 1986 | |
4603403 | Toda | Jul 1986 | |
4618947 | Tran et al. | Oct 1986 | |
4649522 | Kirsch | Mar 1987 | |
4685089 | Patel et al. | Aug 1987 | |
4707811 | Takemae et al. | Nov 1987 | |
4788667 | Nakano | Nov 1988 | |
4847758 | Olson et al. | Jul 1989 | |
4870622 | Aria et al. | Sep 1989 | |
4875192 | Matsumoto | Oct 1989 | |
4933910 | Olson et al. | Jun 1990 | |
5058066 | Yu | Oct 1991 | |
5126975 | Handy et al. | Jun 1992 | |
5267200 | Tobita | Nov 1993 | |
5268865 | Takasugi et al. | Dec 1993 | |
5280594 | Young et al. | Jan 1994 | |
5305284 | Iwase | Apr 1994 | |
5325330 | Morgan | Jun 1994 | |
5325502 | McLaury et al. | Jun 1994 | |
5335336 | Kametani | Aug 1994 | |
5349566 | Merritt et al. | Sep 1994 | |
5357469 | Sommer et al. | Oct 1994 | |
5363330 | Kobayashi et al. | Nov 1994 | |
5373227 | Keeth | Dec 1994 | |
5379261 | Jones, Jr. | Jan 1995 | |
5392239 | Margulis et al | Feb 1995 | |
5410670 | Hansen et al. | Apr 1995 | |
5452261 | Chung et al. | Sep 1995 | |
5457659 | Schaefer | Oct 1995 | |
5526320 | Zagar et al. | Jun 1996 | |
5675549 | Ong et al. | Oct 1997 |
Number | Date | Country |
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19507562 | Sep 1995 | DEX |
Entry |
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"DRAM 1 Meg.times.4 DRAM 5VEDO Page Mode",, 1995 Dram Data Book,, pp. 1-1 thru 1-30,, (Micron Technology, I). |
"Rossini, Pentium, PCI-ISA, Chip Set", Symphony Laboratories,, entire book. |
"DRAM 1991", Toshiba America Electronic Components, Inc., pp. A-137-A-159. |
"Application Specific DRAM", Toshiba America Electronic Components, Inc., C178, C-260, C 218, (1994). |
"Burst DRAM Function & Pinout", Oki Electric Ind., Co., Ltd., 2nd Presentation, Item 619, (Sep. 1994). |
"Hyper page mode DRAM", 8029 Electronic Engineering 66, No. 813, Woolwich London GB, pp. 47-48, (Sep. 1994). |
"Micron Semiconductor, Inc.", 1994 DRAM Data Book, entire book . |
"Mosel-Vitelic V53C8257H DRAM Specification Shhet, 20 pages, Jul. 2, 1994". |
"Pipelined Burst DRAM", Toshiba, JEDEC JC 42.3 Hawaii, (Dec. 1994). |
"Samsung Synchronous DRAM", Samsung Electronics, pp. 1-16, (Mar. 1993). |
"Synchronous DRAM 2 MEG cx 8 SDRAM", Micron Semiconductor, Inc., pp. 2-43 through 2-8. |
Bursky, D., "Novel I/O Options and Innovative Architectures Let DRAMs Achieve SRAM Performances; Fast DRAMS can be swapped for SRAM Caches", Electronics Design, vol. 41, No. 15, Cleveland, Ohio, pp. 55-67, (Jul. 22, 1993). |
Gowni, S.P. , et al., "A 9NS, 32K.times.9, BICMOS TTL Synchronous Cache RAM with Burst Mode Access", IEEE, Custom Integrated Circuits Conference, pp. 781-786, (Mar. 3, 1992). |
Number | Date | Country | |
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Parent | 457651 | Jun 1995 |