BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing the entire construction of a bus system according to an embodiment;
FIG. 2 is a diagram showing a physical positional relationship between processors and a cache;
FIG. 3 is a diagram showing a connection relationship between the processors and the cache in more details;
FIG. 4 is a diagram showing a more detailed construction of each stage of a pipeline register;
FIG. 5 is a diagram showing a logic of a flow control logic circuit;
FIG. 6 is a diagram for explaining an operation of the pipeline register according to the logic of FIG. 5;
FIG. 7 is a diagram showing a detailed construction of an arbiter;
FIG. 8 is a diagram showing a logic of an arbiter circuit;
FIG. 9A is a diagram showing a first modification; and
FIG. 9B is a diagram showing the first modification.