Bus apparatus, bus system and information transferring method

Information

  • Patent Application
  • 20070198758
  • Publication Number
    20070198758
  • Date Filed
    September 08, 2006
    18 years ago
  • Date Published
    August 23, 2007
    17 years ago
Abstract
A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.
Description

BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a diagram showing the entire construction of a bus system according to an embodiment;



FIG. 2 is a diagram showing a physical positional relationship between processors and a cache;



FIG. 3 is a diagram showing a connection relationship between the processors and the cache in more details;



FIG. 4 is a diagram showing a more detailed construction of each stage of a pipeline register;



FIG. 5 is a diagram showing a logic of a flow control logic circuit;



FIG. 6 is a diagram for explaining an operation of the pipeline register according to the logic of FIG. 5;



FIG. 7 is a diagram showing a detailed construction of an arbiter;



FIG. 8 is a diagram showing a logic of an arbiter circuit;



FIG. 9A is a diagram showing a first modification; and



FIG. 9B is a diagram showing the first modification.


Claims
  • 1. A bus apparatus for transferring information between a bus master and a bus slave, comprising: a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; anda plurality of management devices that manage each pipeline register and are provided corresponding to the plurality of pipeline registers, respectively,wherein each of the management devices includes:a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information;an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; anda transfer control unit that determines whether information held by the corresponding pipeline register is transferred based on the holding state of the current stage's pipeline register kept by the holding state keeping unit, and the holding state of the previous stage's pipeline register and the holding state of the subsequent stage's pipeline register specified by the adjacent stage's holding state specifying unit.
  • 2. The bus apparatus according to claim 1, wherein the bus apparatus is connected to a plurality of bus masters and further comprises: an arbiter that selects one pipeline register from among a plurality of pipeline registers corresponding to the plurality of bus masters, and transmits information from a selected pipeline register to a subsequent stage's pipeline register to which information from the plurality of pipeline registers is transmitted,wherein the adjacent stage's holding state specifying unit of the management device provided corresponding to the subsequent stage's pipeline register specifies the holding state of the pipeline register selected by the arbiter as the holding state of the previous stage's pipeline register.
  • 3. The bus apparatus according to claim 2, wherein the arbiter selects the pipeline register based on a holding state of the arbiter, the respective holding states of the plurality of pipeline registers and the holding state of the subsequent stage's pipeline register.
  • 4. The bus apparatus according to claim 3, wherein the arbiter selects a pipeline register based on a history of a past selection by the arbiter.
  • 5. The bus apparatus according to claim 2, wherein the arbiter is positioned near the middle point between a plurality of pipeline registers and the subsequent stage's pipeline register.
  • 6. A bus system comprising: a bas master;a bus slave; anda bus apparatus that transmits information between the bus master and the bus slave,wherein the bus apparatus includes:a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; anda plurality of management devices that manage each pipeline register and are provided corresponding to the plurality of pipeline registers, respectively,wherein each of the management devices contains:a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information;an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; anda transfer control unit that determines whether information held by the corresponding pipeline register is transferred based on the holding state of the current stage's pipeline register kept by the holding state keeping unit, and the holding state of the previous stage's pipeline register and the holding state of the subsequent stage's pipeline register specified by the adjacent stage's holding state specifying unit.
  • 7. The bus system according to claim 6, wherein the bus master determines whether information is send out based on the holding state of a connected pipeline register.
  • 8. The bus system according to claim 6, wherein the bus slave determines whether information is acquired from a connected pipeline register based on whether the bus slave holds information.
  • 9. The bus system according to claim 6, wherein the bus slave determines whether the information is acquired based on the holding state of a connected pipeline register.
  • 10. An information transferring method in a bus apparatus for transferring information between a bus master and a bus slave, wherein the bus apparatus has a plurality of management devices that manage each pipeline register and are provided corresponding to a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing, respectively,each of the management devices specifies a holding state as information indicating whether a previous stage's pipeline register for transmitting information to a current stage's pipeline register corresponding to the management device holds information, and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted, andeach of the management devices determines whether to transfer information held by the corresponding pipeline register based on the holding state of the current stage's pipeline register, which is kept by a holding state keeping unit for keeping a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information, and the holding state of the previous stage's pipeline register and the holding state of the subsequent stage's pipeline register.
Priority Claims (1)
Number Date Country Kind
2006-043182 Feb 2006 JP national