The present invention is related to those disclosed in the following United States Patent Applications: 1. Ser. No. 09/796,328, filed on Feb. 28, 2001, entitled “INTEGRATED CIRCUIT HAVING PROGRAMMABLE VOLTAGE LEVEL LINE DRIVERS AND METHOD OF OPERATION”; 2. Ser. No. 09/796,660, filed on Feb. 28, 2001, entitled “REDUCED NOISE LINE DRIVERS AND METHOD OF OPERATION”; and 3. Ser. No. 09/845,504, filed concurrently herewith, entitled “SPLIT TRANSACTIONAL UNIDIRECTIONAL BUS ARCHITECTURE AND METHOD OF OPERATION”. The above applications are commonly assigned to the assignee of the present invention. The disclosures of these related patent applications are hereby incorporated by reference for all purposes as if fully set forth herein.
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