Claims
- 1. An information processing system comprising:
- a first bus which employs a split bus protocol;
- a first module coupled to said first bus, wherein the first module has a predetermined identifier assigned thereto;
- a first bus adapter coupled to said first bus;
- a second bus coupled to said first bus adapter, wherein the second bus employs the split bus protocol and has a different hierarchy from said first bus; and
- a second bus adapter coupled to said second bus, for enabling a plurality of devices to couple to said second bus, each device having a predetermined identifier for controlling data transfer from said first module to anyone of said devices based on said identifier of each said device.
- 2. The information processing system according to claim 1 wherein said first module is a processor.
- 3. The information processing system according to claim 1 wherein said first bus enables coupling to a plurality of processors.
- 4. The information processing system according to claim 1 wherein each of said identifiers of each device corresponds to an address cache of said device.
Parent Case Info
This application is a continuation application of U.S. Ser. No. 08/544,727, filed Oct. 18, 1995 U.S. Pat. No. 5,671,371 now abandoned; which was a continuation application of U.S. Ser. No. 08/016,692, filed Feb. 11, 1993, now abandoned.
US Referenced Citations (21)
Non-Patent Literature Citations (1)
Entry |
"Futirebis+ P896.1: Logical Layer Specifications," IEEE, 1990, pp. 89-90; and Abstract page May 16, 1991. |
Continuations (1)
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Number |
Date |
Country |
Parent |
544727 |
Oct 1995 |
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