Bus system, bus slave and bus control method

Abstract

A bus system includes one or more bus masters, one or more bus slaves, and a response unit. When an access request to a resource of a bus slave is sent from a bus master, the response unit outputs a wait response that is either a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause it to perform a non-blocking wait operation to the bus master if the bus slave is in the wait state.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing the configuration of a bus system according to an embodiment of the present invention;

FIG. 2 is a view showing a detail of the connection between a bus master and a bus slave in the bus system shown in FIG. 1;

FIG. 3 is a block diagram showing the configuration of a bus slave in the bus system shown in FIG. 1;

FIG. 4 is a flowchart showing the process in the bus slave 50 shown in FIG. 3;

FIG. 5 is a view to describe a detail of the processing performed in the bus system shown in FIG. 1;

FIG. 6 is a view to describe a pipeline processing;

FIG. 7 is a view to describe a non-blocking wait operation:

FIG. 8 is a view to describe a blocking wait operation; and

FIG. 9 is a view to describe a technique according to a related art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.

An exemplary embodiment of the present invention is described hereinafter with reference to the drawings.

FIG. 1 shows a bus system 100 according to a first embodiment of the present invention. The bus system 100 includes bus masters 10, 20, . . . , a bus 30, and bus slaves 50, 60, . . . . The bus masters 10, 20, . . . and the bus slaves 50, 60, . . . are connected to be communicable with each other through the bus 30.

The bus masters 10, 20, . . . are the units which are capable of accessing a resource of a bus slave, such as CPU and DMAC. The bus slaves 50, 60, . . . are the units which are capable of receiving an access request to its resource from a bus master and sending a response thereto, such as I/O device. The DMAC may serve as both a bus master and a bus slave. Alternatively, some CPU may serve as a bus slave in the bus system where a plurality of CPUs are connected. Although FIG. 1 illustrates two bus masters, 10 and 20, and two bus slaves, 50 and 60, the number of bus masters and bus slaves may be any arbitrary number or one of above.

The bus system 100 is described hereinafter with the bus master 10 and the bus slave 50 taken as examples.

FIG. 2 shows a detail of the connection between the bus master 10 and the bus slave 50. The bus 30 includes a control signal line 31, an address line 32, a command line 33, a data line 34, and a response signal line 35. In the following description, the case where the bus master 10 accesses the bus slave 50 for the execution of a load instruction is described by way of illustration.

The bus master 10 sends a request signal REQ to request processing to the bus slave 50 through the control signal line 31. When sending the request signal, it also sends an address ADS and a command CMD (which is a load command in this example) indicating the contents of the processing requested to the bus slave through the address line 32 and the command line 33, respectively.

The bus slave 50 receives the request signal REQ through the control signal line 31 and obtains the address ADS and the command CMD through the address line 32 and the command line 33, respectively. The bus slave 50 decodes the obtained address ADS and determines whether it is the address of a resource of its own. If it is the address of a resource of its own, the bus slave 50 sends a response RESP through the response signal line 35.

The response RESP which is sent from the bus slave 50 is either a ready (RDY) response indicating that the bus slave 50 is ready to perform the requested processing or a wait response indicating that it is not ready. In this embodiment, the wait response from the bus slave 50 further falls into two types, which are described in detail later.

The bus slave 50 executes the requested command CMD when it is in the RDY state. Because the command CMD is a load command in this example, the bus slave 50 loads data DAT at the address which is designated by the address ADS and outputs it through the data line 34.

When the bus master 10 receives the RDY response from the bus slave 50 through the response signal line 35, it retrieves the data DAT which is output from the bus slave 50 through the data line 34.

The operation when the bus master 10 receives the wait response through the response signal line 35 is described later in conjunction with the detail of the bus slave 50.

FIG. 3 shows the configuration of the bus slave 50. The bus slave 50 includes an address decoder 52, a response unit 54, and a register group 58. The response unit 54 includes a response generator 55 and a controller 56. The signals REQ ADS and CMD in FIG. 3 are input from a corresponding signal line of the bus 30 shown in FIG. 2, which is the control signal line 31, the address line 32, and the command line 33. The signals DAT and RESP are output to the corresponding data line 34 and the response signal line 35 of the bus 30 shown in FIG. 2.

FIG. 4 is a flowchart showing the operation when the bus slave 50 receives a request signal REQ from the bus master 10.

The address decoder 52 decodes the address ADS which is sent with the request signal REQ from the bus master 10, determines if the address indicates a resource of the bus slave 50 to which it belongs, and outputs the determination result to the response unit 54 (S10, S20).

In the example of FIG. 3, the bus slave 50 includes the register group 58 that includes a plurality of registers, which serve as resources of the bus slave 50.

The response generator 55 of the response unit 54 ends the process if the signal from the address decoder 52 does not indicate an access request to the resource of its own (No in S20). If, on the other hand, the signal from the address decoder 52 indicates an access request to the resource of its own, the response generator 55 receives the request signal REQ, the address ADS and the command CMD and checks the type of the register corresponding to the address ADS (Yes in S20, S30).

There are two types of registers; one is a register which requires the blocking wait operation and the other is a register which does not require the blocking wait operation.

A technique for the response generator 55 to check the type of a register may be any mechanism as long as it can determine whether a register requires the blocking wait operation or not. For example, a table which correlates a register with whether the register requires the blocking wait operation may be prepared, so that the response generator 55 can make a decision by referring to the table. Alternatively, when an address contains 16 bits, the low-order 4 bits may be used to indicate whether a register requires the blocking wait operation, so that the response generator 55 make a decision by referring to the low-order 4 bits of the address which is sent from the address decoder 52.

The response generator 55 outputs a check result in the step S30, which is information indicating the type of a register to which an access is requested, the address ADS and the command CMD to the controller 56 (Yes in S20, S30, S40).

The controller 56 determines if the requested processing is executable (S50). The determination is made by referring to a counter (not shown) indicating the number of commands which are currently processed. If the requested processing is executable (Yes in S50), the controller 56 outputs a RDY response indicating that the processing is executable through the response signal line 35 and executes the requested processing on the relevant register (S60). For example, if CMD is a load command, the controller 56 loads data from the relevant register and, upon completing the data loading, outputs a signal indicating the processing completion to the bus master 10. The controller 56 outputs the loaded data to the data line 34 and also outputs a RDY response to the response signal line 35.

The bus master 10 retrieves data from the data line 34 in response to the RDY response from the controller 56 of the bus slave 50. Upon receiving the signal indicating the processing completion, the bus master 100 performs the execution completion process and write-back to its own resource and thereby ends the instruction.

On the other hand, if the requested processing is not executable (No in S50), the controller 56 sends a blocking wait response or a non-blocking wait response to the bus master 10 according to the type of a resource sent from the response generator 55. Specifically, if the register to which an access request is made is a register that requires the blocking wait operation, the controller 56 sends a blocking wait response (Yes in S70, S80). If, on the other hand, the register to which an access request is made is a register that does not require the blocking wait operation, the controller 56 sends a non-blocking wait response (No in S70, S90).

The bus master 10 performs the blocking wait operation when it receives the blocking wait response and performs the non-blocking wait operation when it receives the non-blocking wait response.

Although it is not shown in the flowchart of FIG. 4, if an exception occurs during the execution of the requested processing, the bus slave 50 sends an exception response (exp) indicating abnormal completion to the bus master 10. When the bus master 10 receives the exception response, it does not carry out write-back to its own resource in order to perform the exception processing even though it obtains the data which is retrieved during the execution of the processing by the bus slave 50 prior to the exception response.

FIG. 5 shows a detailed example of the processing which is performed in the bus system 100 shown in FIG. 1.

The charts A, B, C and D in FIG. 5 are the timing charts when the bus master 10 executes each stage of the instructions 1 to 5, the contents of a request which is sent from the bus master 10 in the EX stage of the instructions 1 and 4, data that is retrieved by the bus master 10 when the bus slave 50 becomes ready in the DF stage of the instructions 1 and 4, and a response from the bus slave 50 in the DF stage of the instructions 1 and 4, respectively.

The bus slave 50 responds to the access request in the EX stage of the instruction 1. In this example, like the examples in FIGS. 7 and 8, the bus slave 50 sends a wait response in the fourth and fifth cycles and then sends a ready response in the sixth cycle. As an example, consider the case where the bus slave 50 sends the non-blocking (NBW) response. Receiving the NBW response, the bus master 10 suspends the execution of the instruction and then retrieves data D0 from the bus slave 50 in the sixth cycle in response to the ready response (cf. the chart C). After that, the bus master 10 executes the CM stage for completion and the WB stage for write-back in the seventh and eighth cycles respectively, thereby ending the instruction 1.

The execution of the instructions 2 and 3 is started with a delay of one cycle each from the start of the execution of the instruction 1 (the first cycle). As shown in FIG. 5, while the non-blocking wait response is made in the DF stage of the instruction 1 (the fourth and fifth cycles), the EX stage and the DF stage of the instruction 2 and the ID stage and the EX stage of the instruction 3 are executed. Because the bus master 10 performs the non-blocking operation, the subsequent instructions 2 and 3 are executed in the fourth and fifth cycles when the wait response (NBW in this case) is made in the DF stage of the instruction 1.

This is the same for the instruction 4, and the IF stage and the ID stage are executed in the fourth and fifth cycles.

For the instruction 4, the bus master 10 sends an access request (cf. the chart B) to the bus slave 50 in the EX stage of the sixth cycle and receives a wait response (cf. the chart D) in DF stage of the seventh and eighth cycles. Consider the case where the blocking wait operation (BLW) is sent as an example. As shown in FIG. 5, because the bus master 10 performs the blocking operation in the seventh and eighth cycles in response to BLW, the EX stage of the instruction 5 is suspended.

After that, the wait response to the instruction 4 is released in the ninth cycle, and the bus master 10 retrieves the data D1 from the bus slave 50. With the release of the wait response, the EX stage of the instruction 5 is also executed.

As described above, the bus system 100 of this embodiment checks if each register of the register group 58 of the bus slave 50 is a register which requires the blocking wait operation or not and, only when the register requires the blocking wait operation, it sends a wait response to make the bus slave 50 perform the blocking wait operation. It is thereby possible to minimize the blocking wait operation of the bus master 10 in the bus system 100, which enhances higher performance of the bus system 100.

Further, the bus system 100 of this embodiment causes the bus master to perform the blocking wait operation or the non-blocking wait operation by sending a blocking wait response or a non-blocking wait response. It is thereby possible to switch the operation of the bus master without rewriting the program of the bus master. This has a large advantage in program debugging.

In the process of debugging a program, a certain instruction may be reexecuted for checking in some cases. Therefore, the reexecution of an instruction is sometimes necessary even for a bus slave which does not require the blocking wait operation in actual use. To implement this, a bit indicating whether an exception of a bus slave is enabled or disabled may be used, so that the blocking wait response or the non-blocking wait response is sent as a wait response according to the value of this bit. For example, the blocking wait response is sent when a bus slave is in the state to enable an exception, and the non-blocking wait response is sent when a bus slave is in the state to disable an exception. Then, a bit value is set such that a bus slave is in the state to enable an exception during debugging of a program, thereby causing a bus master to perform the blocking wait operation. This permits the reexecution of an instruction in the event of an exception during debugging. On the other hand, a bit value is set such that a bus slave is in the state to disable an exception during actual use, thereby causing a bus master to perform the non-blocking wait operation. This achieves higher performance of the bus system during actual use.

An exemplary embodiment of the present invention is described in the foregoing. The embodiment is given by way of illustration only, and various changes and modifications may be made without departing from the scope of the present invention. All such changes and modifications as would be obvious to those skilled in the art are intended for inclusion within the scope of the present invention.

For example, although the response unit 54 is placed inside each bus slave in the bus system 100 of the above-described embodiment, the response unit 54 or part of the response unit 54 may be placed outside a bus slave, or a single response unit or part of a response unit may be placed in common among a plurality of bus slaves. When using a response unit which is common among a plurality of bus slaves, the response unit may include a table which correlates each register of each bus slave with its type (whether it requires the blocking wait operation or not), so that the response unit determines if each register of a plurality of bus slaves requires the blocking wait operation by referring to the table and then sends a blocking wait response or a non-blocking wait response according to the determination result.

Further, although the address decoder 52 is placed inside each bus slave in the bus system 100 of the above-described embodiment, the address decoder 52 may be placed outside a bus slave, or an address decoder may be placed in common among a plurality of bus slaves. When using an address decoder which is common among a plurality of bus slaves, a table which correlates an address with a bus slave to which a register corresponding to the address belongs may be placed, so that the address decoder outputs a selection signal to a bus slave to which a register corresponding to an address designated by an access request from a bus master belongs to indicate that the bus slave is designated by referring to the table.

Furthermore, although a wait response is sent in the next cycle of the request signal REQ, and the bus master 10 suspends the execution in the DF stage which is subsequent to the EX stage where the request signal REQ is issued in the example of FIG. 5 for easy implementation and high-speed processing, a system may be configured to send a wait response during the cycle where the request signal REQ is issued.

It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.

Claims

1. A bus system to execute pipeline processing, comprising: a bus slave;a bus master to output an access request to the bus slave; anda response unit to output either one of a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause the bus master to perform a non-blocking wait operation to the bus master as a wait response to cause the bus master to perform a wait operation in response to the access request.

2. The bus system according to claim 1, wherein the access request is made to a resource in the bus slave.

3. The bus system according to claim 2, wherein the response unit outputs the wait response depending on whether the resource to which the access request is made requires a blocking wait operation or a non-blocking wait operation.

4. The bus system according to claim 3, wherein the response unit comprises: a response generator to determine whether the resource to which the access request is made requires a blocking wait operation or a non-blocking wait operation; anda controller to output the wait response based on a result of the determination output from the response generator.

5. The bus system according to claim 1, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed for each of the plurality of bus slaves.

6. The bus system according to claim 2, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed for each of the plurality of bus slaves.

7. The bus system according to claim 3, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed for each of the plurality of bus slaves.

8. The bus system according to claim 4, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed for each of the plurality of bus slaves.

9. The bus system according to claim 5, wherein the response unit is placed inside the bus slave.

10. The bus system according to claim 5, wherein the response unit is placed outside the bus slave.

11. The bus system according to claim 1, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed in common among the plurality of bus slaves and outputs the wait response when a bus slave of the plurality of bus slaves to which the access request is made is in a state to cause the bus master to perform a wait operation.

12. The bus system according to claim 2, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed in common among the plurality of bus slaves and outputs the wait response when a bus slave of the plurality of bus slaves to which the access request is made is in a state to cause the bus master to perform a wait operation.

13. The bus system according to claim 3, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed in common among the plurality of bus slaves and outputs the wait response when a bus slave of the plurality of bus slaves to which the access request is made is in a state to cause the bus master to perform a wait operation.

14. The bus system according to claim 4, wherein the bus slave is configured as a plurality of bus slaves, andthe response unit is placed in common among the plurality of bus slaves and outputs the wait response when a bus slave of the plurality of bus slaves to which the access request is made is in a state to cause the bus master to perform a wait operation.

15. A bus slave in a bus system to execute pipeline processing, comprising: one or more resources; anda response unit to output, in response to an access request to one of the resources from a bus master, a wait response that is either one of a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause the bus master to perform a non-blocking wait operation to the bus master.

16. The bus slave according to claim 15, wherein the response unit outputs the wait response depending on whether the resource to which the access request is made requires a blocking wait operation or a non-blocking wait operation.

17. A bus control method in a bus system to execute pipeline processing, comprising: outputting, as a wait response in response to an access request to a resource of a bus slave from a bus master, either one of a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause the bus master to perform a non-blocking wait operation.

18. The bus control method according to claim 17, wherein the wait response is output depending on whether the resource to which the access request is made requires a blocking wait operation or a non-blocking wait operation.