Patent Application
20080250175
1. Field of the Invention
The present disclosure relates generally to the communication of digital signals via interconnects, and more particularly to the communication of digital signals via two-wire buses.
2. Description of the Related Art
The proper operation of a digital device typically is dependent on reliable transitions in data signals and clock signals. However, the analog effects exhibited by a digital signal due to device features can cause substantial distortion in the transmitted digital signal, thereby inhibiting the reliability and reach of the transmitted digital signal. Interconnects are a particular source of signal degradation and electromagnetic interference (EMI) due to their particular physical and operational characteristics, such as relatively long signal transmission lengths, paired interconnect length mismatches, and lack of substantial shielding.
Two-wire bus interconnects, such as those based on an Inter-Integrated Circuit (12C) standard, typically use an open-drain configuration that enables multiple devices to connect directly to the bus without requiring a separate bus arbitration scheme. However, the combination of the resistors used for the open-drain configuration and the parallel arrangement of the two-wires of the bus creates an RC (resistance-capacitance) circuit, which impedes the rise and fall times of edges in the data and clock signals transmitted via the bus and thus reduces the signal fidelity of the data and clock signals. As the length of cables implementing the I2C standard or other two-wire bus standards continues to grow, the signal degradation issues resulting from the analog characteristics of these standards becomes more acute. To illustrate, the Digital Visual Interface (DVI) and High-Definition Multimedia Interconnect (HDMI) standards each utilize the I2C standard for their Display Data Channel (DDC) standard, which is used by a video source device (e.g., a digital video player) to obtain the extended display identification data (EDID) from a video sink device (e.g., a video display). Due to the increasing length of DVI/HDMI cables being implemented and the resulting decrease in signal fidelity, it becomes more likely that the video source device will be unable to obtain accurate EDID from the video sink device, thereby causing the video source device to default to display characteristics (e.g., display resolution) that are of a lower quality than otherwise could be supported by the video sink device. Accordingly, an improved technique for two-wire bus communications would be advantageous.
The present disclosure may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference symbols in different drawings indicates similar or identical items.
In a first aspect, an apparatus can include a plurality of conductive interconnects, and a first cable receptacle including a first housing, and a first receptacle interface coupleable to an interface of a first device and including a first pin interface coupleable to a first line of a first two-wire bus of the first device and a second pin interface coupleable to a second line of the first two-wire bus. The apparatus can also include a first bus interface including a first open-terminal port coupleable to the first line of the first two-wire bus via the first pin interface and a second open-terminal port coupleable to the second line of the first two-wire bus via the second pin interface, a second bus interface including a first push-pull port coupled to a first conductive interconnect of the plurality of conductive interconnects and a second push-pull port coupled to a second conductive interconnect of the plurality of interconnects, the first conductive interconnect configured as a first line of a second two-wire bus and the second conductive interconnect configured as a second line of the second two-wire bus, and first control logic to communicate information between the first two-wire bus and the second two-wire bus via the first bus interface and the second bus interface.
The term “open-terminal,” as used herein, is defined as a configuration whereby one or more resistive elements are used to drive a bus line to one voltage reference and one or more transistors are used to drive the bus line to another voltage reference. The term “push-pull,” as used herein, is defined as a configuration whereby one or more transistors are used to drive a bus line to one voltage reference or logic level and one or more transistors are used to drive the bus line to another voltage reference or logic level. The term “two-wire bus” and its variants, as used herein, refers to a bus that utilizes two conductive lines to communicate information, such as data and clock information. The conductive lines can include electrically conductive lines (e.g., wire interconnects), optically conductive lines (e.g., fiber optic lines), or a combination thereof. A two-wire bus can include voltage reference lines in addition to the two lines used to transmit information. Further, a two-wire bus can be implemented as part of a larger bus scheme, such as a DDC bus in an DVI/HDMI interconnect.
Reference made to driving a line or a signal to particular state comprises either driving the line or signal to the particular state from another state or maintaining the line or signal at a particular state.
The term “cable,” as used herein, is defined as an assembly of two or more conductive (electrically conductive or optically conductive) interconnects in an enveloping sheath and at least one cable receptacle disposed at a corresponding end of the sheath and electrically or optically coupled to at least a subset of the two or more conductive interconnects. The term “cable adapter,” as used herein, is defined as an assembly of a housing and at least two electrically or optically coupled cable receptacles disposed at the housing. The term “cable receptacle,” as used herein, is defined as a receptacle configured to removably electrically or optically couple and removably mechanically couple with a cable interface of a device or with another cable receptacle. The term “cable assembly,” as used herein, refers to either a cable or a cable adapter. The term “active signal management circuitry” and its variants, as used herein, is defined as circuitry implementing one or more transistor devices configured to manipulate a digital signal. The term “active signal management process” and its variants, as used herein, is defined as a manipulation of a digital signal using active signal management circuitry.
For ease of illustration, the techniques disclosed herein are described in the context of an Inter-Integrated Circuit (I2C) standard-based bus configuration. However, it will be appreciated that the disclosed techniques can be implemented in other open-terminal-based bus configurations using the guidelines provided herein without departing from the scope of the present disclosure. Further, the techniques discloses herein also are described in the context of the transmission of high-definition television (HDTV) related signals, and more specifically, the transmission of signaling based on the digital video interface (DVI) and the high-definition multimedia interface (HDMI) standards. However, it will be appreciated that these techniques can be employed in other signaling environments using the guidelines provided herein without departing from the scope of the present disclosure. Examples of other signal transmission formats in which the disclosed techniques can be implemented include, but are not limited to, a Video Electronics Standards Association (VESA) DisplayPort standard, a Unified Display Interface (UDI) standard, a Serial Attached Small Computer System Interface (SAS) standard, a Serial Management Bus (SMB or SMBus) standard and the like.
Referring to
In the depicted example, the two-wire bus interconnect 104 is configured to emulate an I2C-based bus at the source end and sink end of the data transmission system 100. The two-wire bus interconnect 104 includes an I2C bus segment 108 connected to the source device 102, an I2C bus segment 110 connected to the sink device 106, and an intermediate bus segment 112 connected to the I2C bus segment 108 via a bus adapter device 114 (also referred to herein as bus adapter device A) and connected to the I2C bus segment 110 via a bus adapter device 116 (also referred to herein as bus adapter device B). The I2C bus segment 108 comprises a two-wire bus including a serial data (SDA) line 118 (also referred to herein as the SDAA line) connected to a SDA port (not shown) of the source device 102 and a serial clock (SCL) line 120 (also referred to herein as the SCLA line) connected to a SCL port (not shown) of the source device 106. The I2C bus segment 110 comprises a two-wire bus comprising a SDA line 122 (also referred to herein as the SDAB line) connected to a SDA port (not shown) of the sink device 102 and a SCL line 124 (also referred to herein as the SCLB line) connected to a SCL port (not shown) of the sink device 102. The intermediate bus segment 112 includes a data line 126 and a signal line 128. In some embodiments, some or all of the I2C bus segment 108, the I2C bus segment 110, and the intermediate bus segment 112 further may include voltage reference lines, which are omitted from the illustration of
In one embodiment, the bus adapter device 114 includes an I2C interface 130 comprising an open-terminal port 132 connected to the SDA line 118 and an open-terminal port 134 connected to the SCL line 120, and a bus interface 136 comprising a tristateable push-pull port 138 connected to the data line 126 and a tristateable push-pull port 140 connected to the signal line 128. Similarly, the bus adapter device 116 includes an I2C interface 150 comprising an open-terminal port 152 connected to the SDA line 122 and an open-terminal port 154 connected to the SCL line 124, as well as a bus adapter device bus interface 156 comprising a tristateable push-pull port 158 connected to the data line 126 and a tristateable push-pull port 160 connected to the signal line 128.
For purposes of illustration, the source device 102 is considered to be the master for the two-wire bus interconnect 104 and the sink device 106 is considered to be a slave device for the two-wire bus interconnect 104 in the embodiment of
The use of bus adapter devices 114 and 116 to receive information represented by open-terminal-based signaling, transmit the information, or a representation thereof, via the intermediate bus segment 112 using push-pull-based signaling, and then reconverting the information at the receiving end of the intermediate bus segment 112 to be represented by open-terminal-based signaling can improve signal fidelity while permitting compatibility with source and sink devices configured to support an open-terminal-based signaling standard. The improved signal fidelity can enable the use of longer interconnects than otherwise could be supported using open-terminal-based signaling alone. Example techniques for the conversion of open-terminal-based signaling (e.g., I2C-based signaling) to the push-pull-based signaling of the intermediate bus segment 112 is illustrated in greater detail with reference to
Referring to
Referring to
The open-terminal port 306 is coupleable to an SDA line (e.g., SDA lines 118 or 122,
As discussed above, substantially identical bus adapter devices 300 can be utilized at both the source-side and the sink-side of the two-wire bus interconnect 104 and thus the line of the intermediate bus segment 112 coupled to the tristateable push-pull port 310 is identified as the data line 126 (
The adapter control module 302, in one embodiment, comprises control logic configured to implement one or more state machines or other functions to manipulate the ports 306, 308, 310, and 312 as described herein. The adapter control module 302 includes inputs to receive signaling 360 and 362 from the SDA line and the SCL line, respectively, inputs to receive signaling 364 from one of the data line 126 and the signal line 128 and an input to receive signaling 366 from the other. The adapter control module 302 further includes outputs to provide the control signals 318, 328, 346, and 356 and data signals 344 and 354. Example operations of the adapter control module 302 is described herein with respect to
The clock source 304 includes a clock generation circuit (e.g., an oscillator) or other clock source (e.g., a clock tree, a phase-locked loop, etc.) to provide a clock signal 314 for use by the adapter control module 302. In at least one embodiment, the two-wire bus interconnect 104 (
Referring to
At block 402, an initialization stimulus is received at the bus adapter device 300 and the adapter control module 302 initializes the bus adapter device 300 in response to the initialization stimulus. The initialization stimulus can include, for example, the application of power to the bus adapter device 300 via a voltage reference line of the bus interconnect in which the bus adapter device 300 is implemented. Alternately, the initialization stimulus can include the initiation of a data transaction via the I2C bus segment 108, the I2C bus segment 110, or the intermediate bus segment 112.
At block 404, the bus adapter device 300 determines whether it is associated with a source device, and thus a master-type bus adapter device, or associated with a sink-device, and thus a slave-type bus adapter device. The determination of the bus adapter device 300 as a master-type or a slave-type can be determined on a per-data-transaction basis, or the configuration as master-type or slave-type can be implemented more permanently (e.g., for a succession of data transactions via the two-wire bus interconnect 104). An example technique for making this determination is illustrated herein with reference to
In response to determining that the bus adapter device 300 is a master-type bus adapter device (for a data transaction or for a series of data transactions), the bus adapter device 300 configures itself as a master-type bus adapter device at block 406. Example configurations and operations of a master-type bus adapter device are described in detail herein.
In the I2C standard, the master device typically provides a clock signal via the SCL line of an I2C-type bus. However, because the slave device may need additional time to process incoming write data or to process data in response to a read request, the I2C standard provides for clock stretching (also referred to in the art as synchronization) whereby the slave device can hold the SCL line low until it is ready, at which time the master device continues the clock signal starting at the point at which the slave device pulled the SCL line low. However, some master devices are not enabled to facilitate clock stretching for any of a variety of reasons. Accordingly, at block 408, the bus adapter device 300 determines the clock mode (a clock stretching-enabled mode or a clock stretching-disabled mode) to be implemented by the bus interconnect by determining whether clock stretching is enabled at the source device (as the master device) and the adapter control module 302 configures the bus adapter device 300 to operate in accordance with the determined clock mode. At block 410, the bus adapter device 300 transmits a clock mode indicator to the one or more slave bus adapter devices of the bus interconnect. Example techniques for determining the clock mode and transmitting an indicator of the clock mode are described herein with reference to
At block 412, the bus adapter device 300 enters a transmission mode whereby the bus adapter device 300 is configured to operate as a master-type bus adapter device, such as performing write operations and read operations as a master device based on the clock mode for which the bus adapter device 300 is configured. Example techniques for write operations and read operations are described herein with reference to
Alternately, in response to determining at block 404 that the bus adapter device 300 is a slave-type bus adapter device (for a particular data transaction or a series of data transactions), the bus adapter device 300 configures itself as a slave-type bus adapter device at block 414. Example slave-type bus adapter device configurations and operations are described in detail herein.
At block 416, the bus adapter device 300, as a slave-type device, receives the clock mode indicator transmitted by a master-type bus adapter device (at block 410) and configures itself based on the indicated clock mode. At block 418, the bus adapter device 300 enters a transmission mode whereby the bus adapter device 300 can perform write operations and read operations as a slave device based on the clock mode for which the bus adapter device 300 is configured.
Referring to
In response to an initialization stimulus, each bus adapter device 300 of the bus interconnect (e.g., two-wire bus interconnect 104,
In the event that the bus adapter device 300 determines, via its open-terminal port 306, that a data transaction is being initiated at the I2C bus segment and thus the bus adapter device 300 is associated with the master, or source, device, at block 506 the bus adapter device 300 identifies itself as the master-type bus adapter device and identifies the line of the intermediate bus segment connected to the tristateable push-pull port 312 as the signal line 128 and the line of the intermediate bus segment connected to the tristateable push-pull port 310 as the data line 126. Accordingly, at block 506 the bus adapter device 300 drives the data line 126 to a low logic level for a predetermined duration via its tristateable push-pull port 310 and drives the signal line 128 to a high logic level via its tristateable push-pull port 312. As discussed below, by driving the data line 126 low for the predetermined duration, the master-type bus adapter device signals to the other bus adapter device that it is the master and thus the other bus adapter device is a slave-type bus adapter device. The process then continues to block 406 of the method 400 of
In the event that the bus adapter device 300 does not detect that the initiation of a data transaction at its associated I2C segment at block 504, at block 508 the bus adapter device 300 determines whether a data transaction has been initiated over the intermediate bus segment connected to its tristateable push-pull port 312 by another bus adapter device. In one embodiment, the bus adapter device 300 determines that a data transaction is being initiated on the intermediate bus segment by determining, via one of its push-pull ports, that the data line 126 has been driven to a low logic value for at least the predetermined duration discussed above. If not, the bus adapter device 300 enters an idle state and the process of blocks 504 and 508 repeats until the initiation of a data transaction is detected.
As noted above, the master-type bus adapter device drives its tristateable push-pull port 310 low in response to determining that it is the master-type bus adapter device. Thus, in the cross-coupled configuration of
Referring to
In the timing diagram 700, the source SCL signal 702 represents a clock signal that would be provided by the master device (e.g., source device 102,
The bus adapter device 300 associated with the master device receives a SCL signal initially similar to the source SCL signal 702, whereby the clock cycles of the SCL signal from the master device initially have a first phase (e.g., a low state) and a second phase (e.g., a high state) equal to the first phase 712 and the second phase 714, respectively, of the source SCL signal 702. At block 602 of the method 600, the adapter control module 302 of the bus adapter device 300 determines the duration L (duration 716,
At the end of the second phase a clock cycle of the received SCL signal (e.g., in response to the edge transition 720 at time t2 marking the end of the second phase), the adapter control module 302 configures, via the control signal 326, the pull-down transistor 326 to drive the SCL line low for a duration X (duration 722) between time t2 and time t4, (whereby X=L+A*H, 0<A<1), thereby simulating a clock-stretching operation that would be performed by a slave device. At block 608, the adapter control module 302 configures, via the control signal 326, the pull-down transistor 326 to release the SCL line at the end of duration X at time t4, which allows the resistive element 330 (
A master device that enables clock stretching in accordance with the I2C standard ensures that each phase of the SCL clock signal is fully implemented once clock stretching by a slave device is terminated. Thus, as illustrated by the stretching enabled SCL signal 706, a clock-stretching enabled master device would drive the SCL line high for the full duration H of the second phase of a clock cycle between time t4 and time t7 in response to the SCL line being released by the bus adapter device 300 at time t4. Conversely, a master device that does not enable clock stretching continues to attempt to maintain the periodic clock signaling represented by the source SCL signal 702, and thus drives the SCL line high for only a partial duration H′ between time t4 and t5. Thus, in a clock-stretching enabled configuration, the edge transition 728 at the end of the first clock cycle phase to follow the release of clock stretching would occur after the edge transition 730 of the source SCL signal 702, whereas, in a clock-stretching disabled configuration, the edge transition 732 at the end of the first clock cycle phase to follow the release of clock stretching would occur at the same time at the edge transition 730.
Accordingly, further at block 608, the adapter control module 302 samples the received SCL signal at time t6 at the end of duration Y (i.e., at the end of duration 726 from time t2) to determine the state of the received SCL signal at time t6. In one embodiment, the process of blocks 606 and 608 can be repeated for a number of times in succession to generate a plurality of sampled states of the received SCL signal so as to reduce an incorrect mode detection due to glitches or other perturbations. At block 610, the adapter control module 302 determines whether the sampled value or sampled values of the received SCL signal are equal to the value expected if clock stretching is enabled. To illustrate using the timing diagram of
If the sampled value is equivalent to the expected clock-stretching enabled value, at block 614 the bus adapter device 300 identifies the clock mode of the master device as facilitating clock stretching at block 614 and configures itself to operate in a clock stretching-disabled mode as described herein. Otherwise, the bus adapter device 300 identifies the master device as failing to facilitate clock stretching at block 616 and configures itself to operate in a clock stretching-disabled mode as described herein. In implementations whereby the process is repeated multiple times to generate multiple sampled states of the SCL line, the majority of the comparison results can be used to determine the clock mode of the master device to improve error tolerance. A clock mode indicator indicating the identified clock mode then can be transmitted to the other bus adapter device as described herein.
Referring to
In the example of
At block 802, the source device 102 initiates a transaction by driving the SDA line 118 low at t0 (thereby indicating a start condition) and then transmits address information 914 (e.g., address data bits, a read/write bit) in the SDAA signal 904 while cycling the SCLA signal 902 on the SCL line 120 accordingly. At the end of the address transmission, the source device 102 pulses the SDAA signal 904 at time t1 while the SCLA signal 902 is high, thereby indicating the termination of the address operation. In response to the termination of the address operation, the bus adapter device 114 drives the data line 126 low at time t1. In response to the data line 126 being driven low, the bus adapter device 116 identifies itself as the slave and ceases driving the signal line at block 806.
At block 808, the bus adapter device 114 drives the signal line 128 with a clock mode indicator value (e.g., clock stretching enabled=high; clock stretching disabled=low) representing the clock mode identified at block 408 of method 400 (
In one embodiment, the bus adapter device 116 then uses the sampled value to set the clock mode at the bus adapter device 116 at block 814. However, in certain instances, a glitch may occur that causes a corrupted value to be sampled. Accordingly, to improve error recovery capabilities, the bus adapter device 114 maintains the clock mode indicator value on the signal line 128 from time t2 to time t6, during which time the data line 126 is pulsed N times (e.g., at times t3, t4, and t5), and the bus adapter device 116 samples the clock mode indicator value from the signal line 128 in response to each of the N pulses, thereby generating N sampled clock mode indicator values. The bus adapter device 116 then can more accurately identify the correct clock mode indicator value at block 814 by, for example, using the majority of the N sampled clock mode indicator values as the correct clock mode indicator value. This multiple redundancy therefore allows the clock mode communication process to be more tolerant of glitches that may occur.
Referring to
For ease of illustration, the write operation process is described in the bus interconnect context of
At block 1006, the bus adapter device 114 receives the SDAA signal 1204 representing the bit to be transmitted from the source device 102 via the open-terminal port 136 (open-terminal port 306,
At block 1104, the bus adapter device 116 receives the data information represented by the data signal 1208 via the push-pull port 160 (push-pull port 312,
Referring to
At block 1306, the bus adapter device 114 receives the data signal 1506 via the push-pull port 138 (push-pull port 310,
At block 1406, the bus adapter device 116 receives the SDAB signal 1510 representative of the read bit data via the open-terminal port 122 (open-terminal port 308,
As
Referring to
The term “handshake information,” as used herein, refers to the communication of handshake indicators via an intermediate two-wire bus interconnect. While handshake information is based on clock information (e.g., a received SCL signal), it is not solely based on clock information, but instead is also based on other states of the system in which it is implemented, as described herein. Thus, handshake information is not merely a reproduction of a clock signal, such as the transmission of a buffered clock signal or an inverted clock signal. Likewise, while the communication of clock information can be based on handshake information as described herein, clock information is not merely a reproduction of handshake information, such as the retransmission of received handshake indicators, etc.
The state machine diagram 1600 of the bus adapter device 114 includes states 1602, 1604, 1606, and 1608 (also referred to herein as states MW1-MW4, respectively). The state machine diagram 1650 of the bus adapter device 116 includes states 1652, 1654, 1656, 1658 and 1660 (also referred to herein as states SW1-SW5). Initially at state 1602, the bus adapter device 114 is not driving the SCL line 120 (SCLA) and the source device 102 is driving the SCL line 120 low. Initially at state 1652, the bus adapter device 116 is driving the SCL line 124 (SCLB) low and passing the unknown data value at the data line 126 to the sink device 106 via the SDA line 122 (SDAB). At time t0, the source device 102 drives a bit value onto the SDA line 118 (SDAA) and at time t1, the source device 102 releases the SCL line 120 (SCLA) so that it goes high. The bus adapter device 114 drives the received bit value of the SDA line 118 onto the data line 126.
In response to the SCL line 120 going high, the bus adapter device 114 enters state 1604, whereby the bus adapter device 114 transmits a handshake indicator via the signal line 128. In the illustrated example, handshake indicators are represented by signal pulses on the signal line 128. In order to generate the signal pulse representing the handshake indicator at time t2, the bus adapter drives the signal line 128 at time t2 for a duration sufficient to be detected by the bus adapter device 116 and then tristates its push-pull port 140 (as represented by the “X” boxes in signal 1706) at time t3 so that it can act as a receiver with respect to the signal line 128. For ease of discussion, the driving of the signal line 128 high for a duration sufficient to be detected by the other bus adapter device is referred to herein as “pulsing” the signal line 128 and the resulting effect is referred to herein as a “signal pulse” on the signal line 128. Although handshake indicators are illustrated herein as signal pulses, other handshake indicators, such as edge transitions on the signal line 128, may be used without departing from the scope of the present disclosure.
In response to detecting the handshake indicator (e.g., signal pulse) on the signal line 128 at time t2, the bus adapter device 116 enters state 1654 whereby the bit value on the data line 126 is latched by the bus adapter device 116 and driven onto the SDA line 122 for receipt by the sink device. The sink device 106 can stretch the clock signal so as to process the received bit by driving the SCL line 124 (SCLB) low until processing is substantially complete at time t5. Accordingly, at time t4 the sink device 106 releases the SCL line 124, thereby causing the SCL line 124 to be pulled high. In response to the SCL line 124 being pulled high, the bus adapter device 114 enters state 1656, whereby the bus adapter device 116 transmits a second handshake indicator by pulsing the signal line 128 at time t6 and then the bus adapter device 116 tristates its push-pull port 160 so as to configure the bus adapter device 116 as a receiver with respect to the signal line 128. Further, in state 1656 the bus adapter device 116 continues to drive the latched bit value from the data line 126 onto the SDA line 122 (SDAB).
At some point (time t4 in the timing diagram 1700), the source device 102 drives the SCL line 120 (SCLA) low, thereby causing the bus adapter device 114 to enter state 1606 whereby the bus adapter device 114 holds the SCL line 120 low. In response to detecting the second handshake indicator on the signal line 128 at time t6, the bus adapter device 114 enters state 1608, whereby the bus adapter device 114 transmits a third handshake indicator by pulsing the signal line 128 at time t7 and then the bus adapter device 114 tristates its push-pull port 140 so as to act as a receiver. Further, the bus adapter device 114 continues to hold the SCL line 120 low, thereby stretching the clock at the source device 102.
When entering state 1656 at time t6, the bus adapter device 116 initiates a timer that waits for the minimum SCL high time (MinHigh) specified by the I2C standard or other applicable standard. When both the MinHigh timer has lapsed in state 1656 and the bus adapter device 116 has detected the third handshake indicator (e.g., the signal pulse on the signal line 128 at time t7), the bus adapter device 116 drives the SCL line 124 (SCLB) low and enters state 1658. In state 1658, the bus adapter device 116 initiates a time that waits for the minimum SCL low time (MinLow) specified by the I2C standard or other applicable standard. When the MinLow timer lapses in state 1658, the bus adapter device 116 enters state 1660, whereby the bus adapter device 116 transmits a fourth handshake indicator by pulsing the signal line 128 at time t8, tristates its push-pull port 160, and then returns to state 1652 at time t9. When the bus adapter device 114 detects the pulse on the signal line 128 at time t8 while in state 1608, the bus adapter device 114 returns to state 1602. The technique of waiting for both the expiration of MinHigh and MinLow aids in ensuring that the SCLB signal 1712 meets the critical timing specifications of the I2C standard even when the SCLA signal 1702 is operating under a faster specification. Further, waiting for both the expiration of MinHigh and MinLow prevents the transmission of data by the source device from getting ahead of the reception of the data by the sink device.
Referring to
When entering state 1852, the bus adapter device 116 initiates a MinLow timer (described above) at time t0 to ensure that the SCL line 124 is driven low for a time sufficient to meet I2C specifications or other specifications. When the MinLow timer has lapsed at time t1, the bus adapter device 116 releases the SCL line 124 (SCLB) and enters state 1854. When the sink device 106 is ready to supply the read bit value, the sink device 106 drives the read bit value onto the SDA line 122 (SDAB) and releases the SCL line 124 (SCLB), thereby allowing the SCL line 124 to go high at time t3. The bus adapter device 116 drives the read bit value from the SDA line 122 (SDAB) onto the data line 126 via the push-pull port 160. In response to the SCL line 124 (SCLB) going high at time t3, the bus adapter device 116 enters state 1856, whereby the bus adapter device 116 transmits a first handshake indicator by pulling the signal line 128 at time t4.
After detecting the first handshake indicator on the signal line 128 at time t4, the bus adapter device 114 enters state 1804, whereby the bus adapter device 114 releases the SCL line 120 (SCLA), latches the read bit value on the data line 126, and begins driving the latched read bit value onto the SDA line 118 (SDAA). When the source device 102 drives the SCL line 120 (SCLA) high at time t5, the actual bit transfer is initiated and the bit value on the SDA line 118 is latched at the source device 102 for processing at the source device 102. In response to the SCL line 120 (SCLA) being driven high, the bus adapter device 114 enters state 1806, whereby the bus adapter device 114 continues to latch the read data bit onto the SDA line 118 and transmits a second handshake indicator by pulsing the signal line 128 at time t6.
At some point (e.g., time t7 in the timing diagram 1900), the source device 102 pulls the SCL line 120 (SCLA) low, thereby causing the bus adapter device 114 to enter state 1808, during which the bus adapter device 114 holds the SCL line 120 low.
Upon entering state 1856, the bus adapter device 116 initiates the MinHigh timer (discussed above). Upon the lapse of the MinHigh timer and in response to detecting the second handshake indicator on the signal line 128 at time t6, the bus adapter device 116 enters state 1858. In state 1858, the bus adapter device 116 drives the SCL line 124 (SCLB) low and at time t8 transmits a third handshake indicator by pulsing the signal line 128. In response to detecting the third handshake indicator on the signal line 128, the bus adapter device 114 enters state 1810 whereby the bus adapter device 118 transmits a fourth handshake indicator by pulsing the signal line 128 at time t9 and then returns to state 1802 at time t O. In response to detecting the fourth handshake indicator on signal line 128, the bus adapter 116 enters state 1852, initiates the MinLow timer and continues to drive the SCL line 124 (SCLB) low.
As illustrated by
Referring to
The bus adapter device 114, as the master-type bus adapter device, typically initiates communications with the bus adapter device 116. However in certain implementations, it may be advantageous to facilitate the initiation of communications by the bus adapter device 116. The timing diagram 2000 illustrates an example technique.
In an idle condition, the bus adapter device 114 drives the data line 126 high and the bus adapter device 116 drives the signal line 128 high. To initiate a communication, a request signal 2016 is pulsed at time t1. The request signal 2016 can be generated by the bus adapter device 116 in response to, for example, the loss of PLL lock or the loss of EMI encoding synchronization at the bus adapter device 116, and the like. In response to the pulse in the request signal 2016 at time t1, the bus adapter device 116 generates a sequence of N low pulses on the signal line 128. In the illustrated example, the bus adapter device 116 generates a sequence of three (N=3) low pulses, pulses 2020, 2022, and 2024, at times t1, t2, and t3, respectively. In at least one embodiment, the pulses have a duration sufficient to be detected by the bus adapter device 114.
In response to detecting the predetermined number N of low pulses on the signal line 128 while in an idle state (using, e.g., a counter at the adapter control module 302,
Referring to
The multimedia source device 2102 includes a DVI/HDMI interface 2108 to provide video, clock and control information to the multimedia display device 2106 and to obtain control information from the multimedia display device 2106. The DVI/HDMI interface 2108 therefore includes one or more ports 2110 to transmit video information and a port 2112 to transmit a pixel clock (e.g., as transition-minimized differential signaling), and a display data channel (DDC) module 2114 to communicate control information between the multimedia source device 2102 and the multimedia display device 2106 via the two-wire bus interconnect 2104. The control information can include, for example, extended display information data (EDID) and/or high-bandwidth digital copyright protection (HDCP) data communicated to or from the multimedia display device 2106. In at least one embodiment, the DDC module 214 acts as the master device for a two-wire bus 2116 of the two-wire bus interconnect 2104.
The multimedia display device 2102 includes a DVI/HDMI interface 2118 to receive video information via one or more ports 2120 and the pixel clock 2120 via a port 2122. The DVI/HDMI interface 2118 further includes an EDID module 2124 and an HDCP module 2126 that act as slave devices for the two-wire bus 2116. The EDID module 2124 is configured to provide EDID information to the DDC module 2114 in response to read operations to the EDID module 2124 initiated by the DDC module 214 via the two-wire bus 2116 and the HDCP module 2124 is configured to receive HDCP information from the DDC module 2114 and provide HDCP information to the DDC module 214 in response to write operations and read operations, respectively, initiated via the two-wire bus 2116.
In at least one embodiment, the DVI/HDMI interface 2108 and the DVI/HDMI interface 2118 are configured to interface with an I2C-based bus interconnect, as is provided by the DVI and HDMI specifications. However, due to the potential lengths of the two-wire bus, the use of a conventional I2C bus using open-terminal-based signaling across the entire length of the two-wire bus can result in signal degradation sufficient to prevent the DDC module 2114 from obtaining accurate EDID information and HDCP information, thereby resulting in a significant degradation in the display quality of the multimedia data transmitted in the multimedia transmission system 2100. To illustrate, even though a display device may be able to support a high resolution display, such as 1080 p, many multimedia source devices are configured to default to a low resolution standard, e.g., 720 p, when they are unable to successfully ascertain the maximum resolution supported by a display device due to a failure to accurately obtain EDID information via the I2C-based bus used for low-speed data transmissions.
In order to improve signal fidelity, and thus facilitate the successful transmission of EDID and HDCP information, the two-wire bus 2116 can implement the bus adapter devices 114 and 116 at the source-end and the sink-end, respectively, as described above. Due to the conversion from open-terminal-based signaling to push-pull-based signaling and back to open-terminal-based signaling, the two-wire bus 2116 can improve signal fidelity over greater interconnect lengths while being compatible with the I2C standard and other open-terminal-based standards at the source and sink ends.
In one embodiment, the two-wire bus interconnect 2104 can be implemented as a cable apparatus that connects the multimedia source device 2102 and the multimedia display device 2106. The cable apparatus can include a cable (e.g., a DVI-compatible cable or an HDMI-compatible cable) having the bus adapter devices 114 and 116 implemented at respective ends of the cable. Alternately, the cable apparatus can include a passive cable (e.g., a conventional HDMI or DVI cable) with cable adapters at both ends, whereby one cable adapter implements the bus adapter device 114 and the other cable adapter implements the bus adapter device 116. Alternately, one or both of the bus adapter devices 114 and 116 can be implemented at the bus interface of the multimedia source device 2102 or the multimedia display device 2106, respectively. In yet other embodiments, various combinations of the bus adapter devices implemented at an end of a cable, at a cable adapter, and at the interface of the source or sink device can be utilized. Cable-based implementations of the bus adapter devices are illustrated herein with reference to
Referring to
For ease of illustration, the high-speed data/pixel clock signals transmitted via the cable 2206 include one or more video data signals represented by signal V+ and its complement signal V− and a pixel clock signal represented by signal CLK+ and its complement signal CLK−. Likewise, the device interface 2202 includes a SDA line 2218 and an SCL line 2220 for transmitting low-speed data in accordance with the I2C standard, a voltage reference signal Vdd and a voltage reference signal GND. Although this particular combination of digital signals is illustrated for ease of discussion, it will be appreciated that the techniques described herein can be utilized for any number or signaling-type of digital signals using the guidelines provided herein.
The bus adapter device 2214, in one embodiment, is configured to convert between the open-terminal-based signaling for the SDA line 2218 and the SCL line 2220 and the push-pull-based signaling of the corresponding data line 2226 (e.g., data line 126,
In the depicted example, the active signal management circuitry 2216 performs one or more active signal management processes on the video and pixel clock signals as described in U.S. patent application Ser. No. 11/519,192, filed on Sep. 11, 2006 and entitled “Active Signal Management in Cables and Other Interconnects,” the entirety of which is incorporated by reference herein. The one or more active signal management processes performed by the active signal management circuitry 2216 on a digital signal can include, but are not limited to, quasi-to-true differential signaling conversion, signal encoding using a noise source, skew management, passive equalization, clock encoding, encryption (e.g., using a data encryption standard (DES), pretty good privacy (PGP) encryption process, elliptical curve algorithms, hash tables or other entropy management or diffusion techniques as appropriate), deserialization and reserialization, periodic symbol encoding, and combinations thereof. The corresponding active signal management process at the receive end so as to recover the original digital signal therefore can include true-to-quasi differential signaling conversion, signal decoding, clock decoding, periodic symbol decoding, skew alignment, decryption, and combinations thereof.
In one embodiment, the active circuitry 2212 is powered by the voltage reference signals transmitted via the cable 2206. However, in certain instances, the device interface 2202 may be unable to source sufficient current or voltage to adequately power the active circuitry 2212. In this instance, the cable 2206 can include a power interface (not shown) to receive adequate power. The power interface can include, for example, a USB interface, a voltage interface to an ADC converter that connects to a standard 115 VAC wall outlet, and the like.
The implementation of the two-wire adaptive circuitry 2214 at one or both cable receptacles 2208 of the cable 2206 provides a number of benefits. In many instances, it may be infeasible to implement the two-wire adaptive circuitry at the source device or the sink device due to cost considerations or compatibility issues. Accordingly, the implementation of the two-wire adaptive circuitry within the cable 2206 itself allows the cable 2206 to be compatible with both the source device and the destination device while still providing for improved signal fidelity for digital signals transmitted via the cable 2206. In other instances, two-wire adaptive circuitry may be implemented at one of the source device and the destination device, but not the other. In this case, the implementation of the corresponding two-wire adaptive circuitry at the other end of the cable 2206 can permit or otherwise facilitate the use of two-wire adaptation process.
To illustrate, assume that the source device employs two-wire adaptive circuitry at its cable interface while the sink device does not have two-wire adaptive circuitry at its cable interface. The sink device, lacking two-wire adaptive circuitry, would be unable to recover the original signal from the altered signal, which would result in an incompatibility between the source device and the sink device. However, if the source device and the sink device were connected using a cable assembly having the two-wire adaptive circuitry at the cable receptacle connected to the sink device, the two-wire adaptive process could be applied by the source device to generate a processed digital signal and the two-wire adaptive circuitry at the cable receptacle at the sink end could receive the processed signal and perform one or more corresponding two-wire adaptive processes to recover the original data and provide the recovered data to the sink device.
Referring to
The cable receptacle 2300 includes a housing 2302 fixed to a cable body 2310, whereby the active circuitry 2212, including the two-wire adaptive circuitry 2214, is disposed within the housing 2302. For purposes of illustration, active circuitry 2212 is illustrated as a single IC, such as an ASIC or FPGA, within the housing 2302. However, it will be appreciated that the active circuitry 2212 can be implemented as multiple discrete circuit devices. The cable receptacle 2300 further includes a receptacle interface 2304 that is removably attachable to a DVI cable interface of the source device or a DVI cable interface of the sink device. The receptacle interface 2304 can be attached to the DVI interface of a corresponding device via mechanical friction between the receptacle interface 2304 and the corresponding receptacle of the DVI interface, via clamps, screws or other mechanical fastening means, and the like.
Disposed at the external face of the receptacle interface 2304 is a pin interface 2306 configured to provide electrical connections between the device-side pins (male or female) of the active circuitry 2212 and the corresponding pins of the DVI interface of the device to which the cable receptacle 2302 is removably attached. In the example of
Referring to
In the depicted example, a device interface 2402 is connected to a conventional passive cable 2404 (e.g., a standard DVI cable) via a cable adapter 2406. The transmit-side cable adapter 408 incorporates the active circuitry 2212, including the two-wire adaptive circuitry 2214 for signal conversion between an SDA line 2418 (e.g., SDA line 118 or SDA line 122,
Referring to
The cable adapter 2500 includes a housing 2502 in which the active circuitry 2212, including the two-wire adaptive circuitry 2214, is disposed. The cable adapter 2500 further includes receptacle interfaces 2504 and 2506 that are removably attachable to the DVI interface of the source device or the sink device and the receptacle interface of the corresponding cable receptacle of the conventional passive cable 2404 (
As illustrated by
In this document, relational terms such as “first” and “second”, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises”, “comprising”, or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
The term “another”, as used herein, is defined as at least a second or more. The terms “including”, “having”, or any variation thereof, as used herein, are defined as comprising. The term “coupled”, as used herein with reference to electro-optical technology, is defined as connected, although not necessarily directly, and not necessarily mechanically.
The terms “assert,” “set,” “negate,” “deassert,” “clear,” “drive,” or “pull” are used when referring to the rendering of a signal, a conductor, or similar apparatus into a particular state. If the logically true state is a high logic high level, the logically false state is a low logic level, or vice versa. Likewise, although the preceding description makes reference to “low” and “high” states for signaling in particular arrangements, it will be appreciated that the arrangement may be reversed as appropriate.
Other embodiments, uses, and advantages of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. The specification and drawings should be considered example only, and the scope of the disclosure is accordingly intended to be limited only by the following claims and equivalents thereof.
The present application is related to the following applications, the entireties of which are incorporated by reference herein: U.S. patent application Ser. No. ______ (Attorney Docket No. 1009-0021), filed on even date herewith and entitled “Adaptive Two-Wire Bus”; U.S. patent application Ser. No. ______ (Attorney Docket No. 1009-0022), filed on even date herewith and entitled “Data Transaction Direction Detection in an Adaptive Two-Wire Bus”; U.S. patent application Ser. No. ______ (Attorney Docket No. 1009-0023), filed on even date herewith and entitled “Clock Mode Detection in an Adaptive Two-Wire Bus”; and U.S. patent application Ser. No. ______ (Attorney Docket No. 1009-0024), filed on even date herewith and entitled “Clock Stretching in an Adaptive Two-Wire Bus”.
