Claims
- 1. A data processing system comprising:
- a main memory for storing a plurality of instructions;
- a processor for executing the instructions, the processor providing a first cache disable signal in response to executing a predetermined one of the instructions;
- a cache memory for temporarily storing a selected subset of the instructions executed by the processor;
- cache disable means for disabling the cache memory in response to the first cache disable signal provided by the processor;
- first means in the cache disable means for receiving a second cache disable signal from a source external to said data processing system;
- second means in the cache disable means for disabling the cache memory in response to the second cache disable signal received by the first means;
- third means in the cache disable means for disabling said second means in response to a control signal provided by the processor while the processor is accessing the cache memory.
Parent Case Info
This is a continuation of application Ser. No. 625,342, filed 6-26-84, now abandoned.
US Referenced Citations (8)
Continuations (1)
|
Number |
Date |
Country |
Parent |
625342 |
Jun 1984 |
|