Patent Application
20250130944
This application claims the priority of Chinese patent application No. 202211593112.3, filed on Dec. 13, 2022, the disclosure of which is hereby incorporated in its entirety as a part of this application.
Embodiments of the present disclosure relate to a cache status recording method, a data access method, and related apparatuses and devices.
CXL (Compute Express Link) interconnection protocol is a protocol for achieving cache coherence between a host and a device, which is used for keeping data cached by a host consistent with data cached by a device, thus avoiding data conflicts in a computing device.
The CXL protocol supports the cache coherence protocol, which is a protocol used for achieving the coherence of data in caches configured by multiple processor cores in a host under a multi-core processor scenario. The cache coherence protocol divides cache data in the caches into a plurality of different statuses to represent the sharing degree of the corresponding cache data by the plurality of processor cores, and performs different operations based on the corresponding statuses. In the CXL protocol, cache data in a cache of a peripheral device is subjected to corresponding status division, and a corresponding operation is performed based on the corresponding status.
Accordingly, when accessing corresponding cache data based on the CXL protocol, it is necessary to record the status of the cache data in the peripheral device, so as to perform the corresponding operation based on the corresponding status. How to record the status of the cache data in the peripheral device is a technical problem that needs to be solved urgently by those skilled in the art.
In view of the above, embodiments of the present disclosure provide a cache status recording method, a data access method and related apparatuses and devices, which can achieve the recording of cache data status in peripheral devices.
To achieve the above objectives, embodiments of the present disclosure provide the following technical solution:
Embodiments of the present disclosure provide a cache status recording method which is applied to a probe filter, wherein a host cache record table is configured in the probe filter, the host cache record table is used for recording a status of cache data of a host in a host cache and a peripheral sharing identifier corresponding to the cache data, the peripheral sharing identifier is used for indicating whether the cache data is shared by a peripheral device, and the method includes:
Optionally, when the peripheral device exclusively owns the cache data, the method further includes:
Optionally, when the peripheral device exclusively owns the cache data, the method further includes:
Optionally, when the processor core exclusively owns the cache data, the method further includes:
Optionally, when the processor core exclusively owns the cache data, and the host cache record table does not include a status of cache data which is to be accessed, the method further includes:
sending a device cache information updating request to a memory controller to update a device cache information in a memory, such that the device cache information indicates that corresponding data in the memory is cached by the peripheral device as invalid.
Embodiments of the present disclosure further provide a data access method, wherein the method is applied to a probe filter, and the method includes:
Optionally, in the access request, the request initiator is the peripheral device, and a device cache request of the peripheral device obtains a sharing permission of the data to be accessed:
Optionally, in the access request, the request initiator is one processor core of a plurality of processor cores, and the processor core requests to acquire an exclusive permission of the data to be accessed:
Optionally, when the cache status of the data to be accessed does not exist in the host cache record table, the processing the data to be accessed based on a permission that the access request to acquire and the information in the host cache record table includes:
Optionally, in the access request, the request initiator is a peripheral device, and the peripheral device requests to acquire an exclusive permission of the data to be accessed:
Embodiments of the present disclosure further provide a computer device which includes a host and a peripheral device,
Optionally, the host cache record table includes status entries corresponding to the cache data in the host one by one, and a status entry includes an address tag, a cache status, a data owner, data distribution, and the peripheral sharing identifier:
Optionally, the peripheral sharing identifier occupies a 1-bit storage space of the status entry.
Optionally, the host computer further includes a memory, wherein device cache information of cache data of the peripheral device is stored in the memory, and the device cache information is used for recording status information of the cache data of the peripheral device.
Optionally, the device cache information is stored in a redundant space of a memory page where memory data corresponding to the cache data is located.
Optionally, the device cache information includes a peripheral sharing identifier, a device cache status and a device cache data owner, the peripheral sharing identifier is used for marking whether the corresponding data in the memory is cached in the peripheral device, the device cache status is used for marking a status of the corresponding data in the memory in the device cache, and the device cache data owner is used for recording a device identifier of the peripheral device that caches the memory data.
Optionally, the memory further includes an error correcting code checksum, and the error correcting code checksum is calculated based on the device cache information and the memory data corresponding to device cache information.
Embodiments of the present disclosure further provide a cache status recording apparatus which applied to a probe filter, wherein a host cache record table is configured in the probe filter, the host cache record table is used for recording a status of cache data of a host in a host cache and a peripheral sharing identifier corresponding to the cache data, the peripheral sharing identifier is used for indicating whether the cache data is shared by a peripheral device, and the cache status recording apparatus includes:
Embodiments of the present disclosure further provide a data access apparatus, comprising:
Embodiments of the present disclosure further provide a storage medium having one or more executable instructions stored thereon, wherein the one or more executable instructions are used for executing the cache status recording method according to the embodiments of the present disclosure, or executing the data access method according to the embodiments of the present disclosure.
The embodiments of the present disclosure provide a cache status recording method, a data access method and related apparatuses and devices. The method is applied to a probe filter, wherein a host cache record table is configured in the probe filter, the host cache record table is used for recording a status of cache data of a host in a host cache and a peripheral sharing identifier corresponding to the cache data, the peripheral sharing identifier is used for indicating whether the cache data is shared by a peripheral device, and the method includes: when the peripheral device shares the cache data in the host cache, updating the peripheral sharing identifier such that the peripheral sharing identifier indicates a corresponding cache data is shared by the peripheral device; and when a processor core exclusively owns the cache data, updating the peripheral sharing identifier such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device.
It can be seen that according to the cache status recording solution and the data access solution provided by embodiments of the present disclosure, based on a peripheral sharing identifier recorded in a host cache record table, a main status that affects a data processing flow can be determined, such that the cache data status can be recorded in the peripheral device, and then a corresponding access flow can be executed based on information in the host cache record table.
To provide a clearer explanation of the technical solution of the disclosed embodiments, a brief introduction will be made to the accompanying drawings required for the embodiments. It is obvious that the accompanying drawings described below are only relates to the disclosed embodiments. For those skilled in the art, other accompanying drawings can be obtained based on the provided drawings without creative labor.
The following will provide a clear and complete description of the technical solution in the disclosed embodiments, in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the disclosed embodiments, not the entire embodiments. Based on the embodiments disclosed in the present disclosure, all other embodiments obtained by ordinary technical personnel in this field without creative labor fall within the scope of protection of the present disclosure.
As mentioned in the background, when accessing corresponding cache data based on the CXL protocol, it is necessary to record the status of the cache data in the peripheral device, so as to perform the corresponding operation based on the corresponding status. How to record the status of the cache data in the peripheral device is a technical problem that needs to be solved urgently by those skilled in the art. Next, a data access flow of a computer device will be described in detail.
With reference to
Where, each processor core is configured with a corresponding host cache, data access is realized by the corresponding host cache: the memory controller is configured to read and send data in a memory to the host cache, or write the data in the host cache into the memory, and all interactions corresponding to the memory are performed by the memory controller: the peripheral controller is configured to control a data access flow by the peripheral device, and all interactions corresponding to the peripheral device are performed by the peripheral controller: the probe filter is configured to record statuses of cache data of processor cores in the host caches based on access requests of buses, and allow the access requests to execute different processing flows based on their recorded statuses of cache data. In an example of the present disclosure, the peripheral controller controls the peripheral device based on the CXL protocol.
The cache data in the cache may include four statuses: M (Modified), E (Exclusive), S (Share) and I (Invalid). Where, M indicates that the cache data is in a modified status, E indicates that the cache data is in an exclusive status, S indicates that the cache data is in a shared status, and I indicates that the cache data is in an invalid status.
In the probe filter, for the host cache, the status of the cache data of the host cache may be recorded through a host cache record table, wherein a corresponding number of status entries may be set in the host cache record table based on space positions of the caches to record the statuses of the cache data of the corresponding cache spaces. An alternative status entry is structurally shown in
In an alternative solution, in order to maintain the cache coherence of the peripheral device, a device cache record table is further set in the probe filter, so as to maintain the coherence between the peripheral device and the cache data in the host based on the device cache record table.
Specifically, in the cache of the peripheral device (also called a device cache), the cache data in the cache may also include four statuses: M (Modified), E (Exclusive), S (Share) and I (Invalid). When the cache status of cache data is M, latest data is only stored in the device cache, and there is no copy elsewhere, such that data have to be acquired from the device cache. When the cache status of cache data is E, latest data is stored in the device cache and the host memory at the same time, and the latest data may be acquired through the host memory or the device cache. When the cache status of cache data is S, latest data exists in the host cache, the host memory and the device cache at the same time, and the latest data may be obtained from any of the host cache, the host memory and the device cache. When the cache status of cache data is I, latest data is not necessarily in the device cache, but may exist in the host cache or the host memory. The peripheral device may silently rewrite the E-status to the M-status locally after obtaining a permission of the E-status, such that the E-status and the M-status may be considered together.
Accordingly, the device cache record table includes status entries corresponding to the device cache space positions one by one, and then based on the corresponding status entries, the maintenance of the cache coherence of the device cache may be realized based on the device cache record table.
It can be seen that in order to record the cache data of the device cache, it is necessary to add a storage space in the probe filter to store corresponding status entries. However, the number of peripheral devices and the corresponding cache space sizes are variable. If the added storage space is too large, the corresponding hardware cost is too high; if the added storage space is too small, the degradation of system performance will be caused due to hardware mismatch. Obviously, this cache recording method for the peripheral device has too many defects.
After studying the status of cache data and the access flow of the corresponding cache data, the inventor considers that whether the cache data in the device cache is cached by the host and shared by the peripheral device and the processor core are main factors that affect its access flow; wherein, since it may be determined whether data can be transferred based on the cache data in the host cache when determining whether the cache data is cached by the host, by determining whether the cache data is shared by the peripheral device and the processor core, it may be determined whether there is a device that shares the cache data when an exclusive permission of the cache data needs to be acquired, and then the cache data in the corresponding device is evicted.
In view of this, the inventor considers that whether the data is cached by the host may be confirmed based on the host cache record table, and at the same time, based on the cache data shared by the peripheral device and the processor core, it is necessarily recorded in the host cache. Therefore, a small amount of adjustment may be performed in the host cache record table to mark whether the corresponding cache data is shared by the peripheral device and the processor core in the host cache record table, and then the processing flow of the corresponding cache data can be determined.
In view of this, embodiments of the present disclosure provide a cache status recording solution and a data access solution. In this solution, a peripheral sharing identifier indicating whether cache data is shared by a peripheral device is added to a host cache record table to record a shared status of the cache data, and then the peripheral sharing identifier is updated when the peripheral device shares the cache data in the host cache, such that the peripheral sharing identifier indicates that the corresponding cache data is shared by the peripheral device: at the same time, when a processor core exclusively owns the cache data shared by the peripheral device, the peripheral sharing identifier is updated, such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device.
It can be seen that according to the cache status recording method provided by the embodiment of the present disclosure, based on a peripheral sharing identifier recorded in a host cache record table, a main status that affects a data processing flow is determined, such that the cache data status may be recorded in the peripheral device, and then a corresponding access flow may be executed based on information of the host cache record table.
Moreover, the cache status recording method provided by the embodiment of the present disclosure does not need to additionally set a device cache record table corresponding to the peripheral device, such that it is unnecessary to increase the storage space for storing the corresponding data, or consider the influence of the number of peripheral devices and the sizes of their cache spaces on a system, thus avoiding the defects caused by adding the device cache record table.
Next, the cache status recording method provided by the embodiment of the present disclosure will be described in detail.
The cache status recording method may be applied to the computer device shown in
With reference to
In a specific example, when the status entry has a redundant bit, the redundant bit of the status entry may be configured as the peripheral sharing identifier: when there is no redundant bit in the status entry, a storage space corresponding to the peripheral sharing identifier may be added as an independent storage bit to record the peripheral sharing identifier.
It is noted that the peripheral sharing identifier is only used for marking whether the cache data is shared by the peripheral device, such that it may be realized with only a small amount of space: for example, a 1-bit storage space may be used for recording, and thus “0)” or “1” recorded by this bit may be used to indicate whether the corresponding cache data is shared by the peripheral device. Compared with additionally setting a device cache record table corresponding to the peripheral device, the embodiment of the present disclosure obviously has less demand for the storage space, and thus the corresponding hardware cost is also lower.
It can be understood that in the status entry shown in
It can be understood that only information corresponding to the cache data in the host cache is recorded in the host cache record table: accordingly, the cache data in the device cache that is not shared by the host cache cannot be reflected in the host cache record table: in order to avoid possible data conflicts, in an alternative example of the present disclosure, status information (also called device cache information) of the cache data in the device cache may be further stored in the memory, for example, exclusive status information, modification status information and the like of the cache data in the device cache. In a specific example, the corresponding device cache information may be stored in a redundant space of the memory to store the status of the cache data of the peripheral device. Original data of the cache data, namely memory data, is stored in the memory. It can be understood that in a data access process, the memory data may be read into the cache as cache data, and accordingly, corresponding device cache information may be configured for the memory data cached in a peripheral cache. In a specific example, the device cache information is stored in the redundant space of a memory page where the memory data is located.
The device cache information may correspond to memory data corresponding to the cache data, wherein one memory address (one memory page may correspond to one memory address) may correspond to one piece of device cache information. By taking an alternative structural diagram of device cache information shown in
It is noted that the shared status corresponding to the cache data that is shared by the device cache and the device cache is recorded based on the peripheral sharing identifier in the host cache record table, and only other statuses corresponding to the cache data may be stored in the device cache information, so as to reduce the complexity of the device cache information.
It can be understood that, when it is necessary to confirm the status of data not shared by the host cache in the device cache, it may be confirmed based on the device cache information stored in the memory.
In a further alternative example, there is also an ECC (Error Correcting Code) checksum in the memory, and the device cache information and the memory data may be subjected to ECC calculation at the same time to obtain the ECC checksum, such that the device cache information and the memory data may be subjected to integrity protection together based on the ECC checksum.
Next, a cache data status recording flow will be further explained in combination with the data access flow, wherein the cache data status recording flow may be implemented based on the probe filter of the computer device and the host cache record table configured in the probe filter. Specifically, an alternative data access flow shown with reference to
Step S100: acquire an access request.
Where, the access request is used for enabling a request initiator to access data to be accessed. The request initiator may be a peripheral device or a certain processor core in the host, and the request initiator may execute its assigned task by initiating an access flow.
It is noted that in an architecture with multiple processor cores, in order to maintain the data coherence, the access request also includes permission information that the request initiator to acquire, which may be, for example, a sharing permission, an exclusive permission, a modification permission: different permission information corresponds to statuses of cache data: for example, when the cache data needs to be shared, the permission information corresponding to the access request is the sharing permission, and after the corresponding cache data is acquired, the status of the cache data is recorded as shared, that is, in a shared status; and other permission information is also like this, which is omitted here in the present disclosure.
It can be understood that the access request also includes address information of data to be accessed, and the address information may be the system address of the data to be accessed, such that specific data to be accessed may be determined based on the address information.
Step S110: inquire whether a cache status of the data to be accessed exists in a host cache record table.
Where, the host cache record table is used for recording a status of cache data of a host in a host cache and a peripheral sharing identifier corresponding to the cache data, and the peripheral sharing identifier is used for indicating whether the cache data is shared by a device cache.
It can be understood that the access request includes the address information of the data to be accessed, and then the host cache record table may be inquired based on the address information.
In an alternative example, status entries corresponding to space positions of the host cache one by one are set in the host cache records, and the status entries may include an address tag, a cache status, a data owner, data distribution and a peripheral sharing identifier of the cache data cached in the corresponding space positions, so as to indicate the status of the cache data of the host in the host cache and whether the corresponding cache data is shared by the peripheral device.
It can be understood that in the status entry shown in
The peripheral sharing identifier is used for indicating whether the cache data is shared by the peripheral device. It can be understood that, on the basis that whether the cache data is shared by the peripheral device is a main factor that affects the data access flow; by only recording whether the cache data is shared by the peripheral device, as little storage space as possible may be occupied on the premise of determining the specific data access flow; thereby reducing the hardware cost as much as possible.
Step S120: process the data to be accessed based on a permission that the access request to acquire and information in the host cache record table.
Based on the information in the host cache record table, it may be determined whether a cache status of the data to be accessed exists in the host cache record table, and if so, it may also be determined whether the corresponding data to be accessed is shared by the device cache.
It can be understood that, since it may be determined whether the data to be accessed can be transferred based on the cache data in the host cache when determining whether the cache data to be accessed is cached by the host, by determining whether the cache data is shared by the peripheral device and the processor core, it may be determined whether there is a deceive that shares the cache data when an exclusive permission of the cache data needs to be acquired, then the cache data in the corresponding device is evicted, and accordingly the corresponding data processing flow may be executed based on the information in the host cache record table.
Accordingly, after executing the corresponding data processing, the status of the cache data may be recorded based on results of the data processing. Specifically, when the peripheral device shares the cache data in the host cache, step S130 is executed.
Step S130: update the peripheral sharing identifier such that the peripheral sharing identifier indicates that the corresponding cache data is shared by the peripheral device.
It is noted that the statement that the peripheral device shares the cache data in the host cache means that step S130 is executed for updating the peripheral sharing identifier, in a case that the request initiator of the access request is the peripheral device, the permission of the corresponding access request for requesting the acquired data to be accessed is a sharing permission, and the peripheral device acquires the data to be accessed based on the corresponding data processing flow:
Accordingly, when the processor core exclusively owns cache data, step S140 is executed.
Step S140: update the peripheral sharing identifier such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device.
Where, the statement that the processor core exclusively owns cache data means that step S140 is executed for updating the peripheral sharing identifier, in a case that the request initiator of the access request is the processor core, the permission of the corresponding access request for requesting the acquired data to be accessed is an exclusive permission, and based on the corresponding data processing flow, the processor core has acquired the data to be accessed and the other processor core or peripheral device has evicted the data to be accessed.
It can be understood that, when the processor core exclusively owns cache data, it needs to determine whether the data to be accessed is shared by the peripheral device based on the information recorded in the host cache record table, so as to determine whether the peripheral device needs to perform a data evicting flow.
In a further example, information that the device cache is in other statuses may be recorded in the memory. Specifically, when the peripheral device exclusively owns cache data, step S150 is executed.
Step S150: send a device cache information updating request to update device cache information in the memory, such that the device cache information indicates that corresponding data in the memory is cached by the peripheral device as exclusive.
It is noted that the statement that the peripheral device exclusively owns cache data means that step S150 is executed for sending a device cache information updating request to the memory controller to update the device cache information, in a case that the request initiator of the access request is the peripheral device, the permission of the corresponding access request for requesting the acquired data to be accessed is an exclusive permission, and based on the corresponding data processing flow, the peripheral device has acquired the data to be accessed and the processor core has evicted the data to be accessed.
Accordingly, the memory controller executes step S160 for updating the device cache information corresponding to the data to be accessed in the memory based on the device cache information updating request.
It can be seen that according to the cache status recording method provided by the embodiment of the present disclosure, based on a peripheral sharing identifier recorded in a host cache record table, a main status that affects a data processing flow can be determined, such that the cache data status may be recorded in the peripheral device, and then a corresponding access flow may be executed based on information of the host cache record table.
It can be understood that since the permissions of data requested by different request initiators are different, the corresponding data access flow and cache data recording method are also different. Next, the data access method and the cache data recording method in the embodiments of the present disclosure are further explained in combination with the permissions of different data initiators and requested data.
Specifically, by taking a device cache request of the peripheral device which is to acquire a sharing permission of the data to be accessed as an example, and with reference to
Step S200: a probe filter acquires an access request of a peripheral device.
In the permission information of the access request, the access request may request to acquire the sharing permission of the data to be accessed. It is noted that in the host, interaction information of the peripheral device is based on a peripheral controller, and the corresponding access request may be issued based on the peripheral controller.
It can be understood that step S200 is a concrete implementation of step S100, and the detailed description may refer to the introduction in step S100.
Step S210: the probe filter inquires whether a cache status of the data to be accessed exists in a host cache record table.
It can be understood that based on the access request of the peripheral device, whether the data to be accessed exists in the host cache and whether the data to be accessed is shared by the device cache may be inquired.
It can be understood that step S210 is a concrete implementation of step S110, and the detailed description may refer to the introduction in step S110.
Step S220: the probe filter processes the data to be accessed based on a permission that the access request to acquire and information in the host cache record table.
In the embodiment of the present disclosure, the access request is a sharing permission for the peripheral device to request to acquire the data to be accessed. It can be understood that when the cache status of the data to be accessed exists in the host cache record table, the processing the data to be accessed may specifically include the following steps.
Step S221: the probe filter sends a data acquisition request to a processor core that caches the data to be accessed, wherein the data acquisition request is used for acquiring the data to be accessed cached by the processor core.
The processor core is a processor core corresponding to the cache in which the data to be accessed is recorded in the host cache record table, which is the processor core 1 illustrated as an example. It can be understood that when the cache status of the data to be accessed exists in the host cache record table, it indicates that the host has cached the data to be accessed, and at the same time, the processor core 1 that has cached the data to be accessed may be determined based on the host cache record table, such that a data acquisition request may be sent to the processor core 1 that has cached the data to be accessed to acquire the corresponding data to be accessed.
Step S222: the processor core 1 responds to the data acquisition request and sends the data to be accessed to the probe filter.
Step S223: the probe filter acquires the data to be accessed sent by the processor core 1.
It can be understood that after the processor core 1 sends the data to be accessed, the probe filter may acquire the corresponding data to be accessed.
Step S224: the probe filter sends the data to be accessed to the peripheral device.
After acquiring the data to be accessed, the probe filter may send the data to be accessed to the peripheral device, such that the peripheral device acquires the data to be accessed.
It can be understood that the above data access flow is used to enable the peripheral device to share the cache data in the host cache: accordingly, after step S224 is executed, an updating process of the host cache record table may also be executed, such that the peripheral sharing identifier in the host cache record table corresponding to the data to be accessed indicates that the corresponding cache data is shared by the peripheral device; specifically, step S130 may be executed for updating the peripheral sharing identifier in the host cache record table corresponding to the cache data of the data to be accessed, such that the peripheral sharing identifier indicates that the corresponding cache data is shared by the peripheral device.
In a further example, by taking one processor core, for example, the processor core 0, of a plurality of processor cores requesting to acquire the exclusive permission of the data to be accessed as an example, and with reference to
Step S300: the probe filter acquires an access request of a processor core 0.
Where, in permission information of the access request, the access request may request to acquire the exclusive permission of the data to be accessed.
It can be understood that step S300 is a concrete implementation of step S100, and the detailed description may refer to the introduction in step S100.
Step S310: the probe filter inquires whether a cache status of data to be accessed exists in a host cache record table.
It can be understood that based on the access request of the processor core, whether the data to be accessed exists in the host cache and whether the data to be accessed is shared by the device cache may be inquired. It is noted that in a computer device with multiple processor cores, one processor core cannot know whether data accessed by said processor core exists in another processor core, thus it is necessary to confirm whether the data to be accessed exists in the host cache and whether the data to be accessed is shared by the device cache based on records in the host cache record table.
It can be understood that step S310 is a concrete implementation of step S110, and the detailed description may refer to the introduction in step S110.
Step S320: the probe filter processes the data to be accessed based on a permission that the access request to acquire and information in the host cache record table.
In the embodiment of the present disclosure, the access request is an exclusive permission for the processor core 0 to request to acquire the data to be accessed. It can be understood that when the cache status of the data to be accessed exists in the host cache record table and the data to be accessed is shared by the device cache, the processing the data to be accessed may specifically include the following steps.
Step S321: the probe filter sends a data processing request to the processor core 1 that caches the data to be accessed and a data eviction request to the peripheral device, wherein the data processing request is used for acquiring the data to be accessed and evicting the corresponding cache data, and the data eviction request is used for evicting the cache data of the corresponding cache.
It can be understood that when the cache status of the data to be accessed exists in the host cache record table, it indicates that the host has cached the data to be accessed: at the same time, when the data to be accessed is shared by the device cache, it indicates that the peripheral device has cached the data to be accessed: accordingly, in order to meet the exclusive permission requested by the access request, the processor core 1 that has cached the data to be accessed may be determined based on the host cache record table, and the data processing request may be sent to the processor core 1 that has cached the data to be accessed and the peripheral device, to acquire the data to be accessed and evict the cache data corresponding to the processor core 1 and the peripheral device.
Step S322: the processor core 1 responds to the data processing request, sends the data to be accessed to the probe filter, and evicts the cache data corresponding to the data to be accessed.
It can be understood that, compared with data transmission between the peripheral device and the processor core, data transmission inside the processor core has obviously shorter delay and higher transmission efficiency, thus the data to be accessed may be sent by the processor core to the probe filter.
Where, the data to be accessed may be sent to the probe filter as a response message, and meanwhile the response message is used for informing the probe filter that the corresponding cache data has been evicted.
Step S323: the peripheral device responds to the data eviction request, evicts the cache data corresponding to the data to be accessed, and sends a response message to the probe filter.
Where, after the processor core sends the data to be accessed to the probe filter, the peripheral device may stop sending the data to be accessed and only execute the corresponding data evicting flow.
The response message is used for informing the probe filter that the corresponding cache data has been evicted.
Step S324: the probe filter acquires the data to be accessed sent by the processor core.
It can be understood that after the processor core sends the data to be accessed, the probe filter may acquire the corresponding data to be accessed.
It is noted that when the peripheral device sends a corresponding response message, the probe filter may receive the response message.
Step S325: the probe filter sends the data to be accessed to the processor core that initiates the access request.
After acquiring the data to be accessed, the probe filter may send the data to be accessed to the processor core, such that the processor core acquires the data to be accessed.
It is noted that after acquiring the data to be accessed, the probe filter still should confirm to send the data to be accessed after receiving the response message from the peripheral device.
It can be understood that the above data access flow is used to enable the processor core to exclusively own the cache data shared by the host cache and the device cache; accordingly, after step S325 is executed, the updating process of the host cache record table may also be executed, such that the exclusive status corresponding to the data to be accessed is recorded in the host cache record table, and the peripheral sharing identifier corresponding to the data to be accessed indicates that the corresponding cache data is not shared by the peripheral device: specifically, step S140 is executed for updating the peripheral sharing identifier in the host cache record table corresponding to the cache data of the data to be accessed, such that the peripheral sharing identifier indicates that the corresponding cache data is not shared by the peripheral device. In step S140, a status of the corresponding cache data in the host cache in the host cache record table may be further updated, such that the status of the cache data in the host cache record table indicates that the cache data is exclusively owned by the processor core.
In a further example, when the cache status of the data to be accessed does not exist in the host cache record table, it is necessary to determine whether there are other statuses in which the data to be accessed is cached by the peripheral device, and corresponding processing is further performed. Specifically, with reference to
Step S326: the probe filter sends a data reading request to a memory controller, wherein the data reading request is used for reading the data to be accessed and device cache information corresponding to the data to be accessed.
In an alternative example, the device cache information is stored in the redundant space of the memory page where the memory data is located, and the data reading request may read the corresponding device cache information while reading the data to be accessed.
Step S327: the memory controller responds to the data reading request and sends the data to be accessed and the device cache information corresponding to the data to be accessed to the probe filter.
Based on the data reading request, the memory controller may execute a reading flow of the corresponding data in the memory.
Step S328: the probe filter inquires the device cache information.
After receiving the device cache information, the probe filter may first inquire the device cache information to determine whether there are other statuses in which the peripheral device caches the data to be accessed, and if so, step S329 is executed: if not, step S331 is executed.
Step S329: the probe filter sends a data eviction request, which is used for requesting the peripheral device to evict the cache data corresponding to the data to be accessed.
Step S330: the peripheral device responds to the data processing request, evicts the cache data corresponding to the data to be accessed, and sends a response message to the probe filter.
The response message is used for informing the probe filter that the corresponding cache data has been evicted.
Step S331: the probe filter sends the data to be accessed to the processor core.
After acquiring the data to be accessed and the response message sent by the peripheral device, the probe filter may send the data to be accessed to the processor core, such that the processor core acquires the data to be accessed.
It can be understood that the above data access flow is used to enable the processor core to exclusively own the corresponding cache data: accordingly, after step S331 is executed, the updating process of the host cache record table may be further executed, such that the exclusive status corresponding to the data to be accessed is recorded in the host cache record table, and the peripheral sharing identifier corresponding to the data to be accessed indicates that the corresponding cache data is not shared by the peripheral device: specifically, step S332 is executed for updating a status of the corresponding cache data in the host cache in the host cache record table, such that the status of the cache data in the host cache record table indicates that the cache data is exclusively own by the processor core. It can be understood that when the status of the cache data in the host cache record table indicates that the cache data is exclusively own by the processor core, then the peripheral sharing identifier of the corresponding data to be accessed is set to indicate that the corresponding cache data is not shared by the peripheral device.
It can be understood that the above data access flow is used to enable the processor core to exclusively own the cache data of the host cache: accordingly, if there are other statuses in which the peripheral device caches the data to be accessed exists in the device cache information, the updating process of device cache information should be executed after step S332 is executed, such that the device cache information indicates that the corresponding data in the memory is cached by the peripheral device as invalid: specifically, step S150 may be executed for sending the device cache information updating request to the memory controller to update the device cache information in the memory, such that the device cache information indicates that the corresponding data in the memory is cached by the peripheral device as invalid. Accordingly, in step S160, the memory controller updates the device cache information corresponding to the data to be accessed in the memory as invalid based on the device cache information updating request.
In a further example, by taking the peripheral device requesting to acquire the exclusive permission of the data to be accessed as an example, and with reference to
Step S400: a probe filter acquires an access request of a peripheral device.
Where, in permission information of the access request, the access request may request to acquire the exclusive permission of the data to be accessed.
It can be understood that step S400 is a concrete implementation of step S100, and the detailed description may refer to the introduction in step S100.
Step S410: the probe filter inquires whether a cache status of data to be accessed exists in a host cache record table.
Based on the access request of the peripheral device, whether the data to be accessed exists in the host cache may be inquired.
It can be understood that step S410 is a concrete implementation of step S110, and the detailed description may refer to the introduction in step S110.
Step S420: the probe filter processes the data to be accessed based on a permission that the access request to acquire and information in the host cache record table.
In the embodiment of the present disclosure, the access request is an exclusive permission for the peripheral device to request to acquire the data to be accessed. It can be understood that when the cache status of the data to be accessed exists in the host cache record table, the processing the data to be accessed may specifically include the following steps.
Step S421: the probe filter sends the data processing request to the processor core that caches the data to be accessed, wherein the data processing request is used for acquiring the data to be accessed and evicting the cache data corresponding to the processor core.
It can be understood that when the cache status of the data to be accessed exists in the host cache record table, it indicates that the host has cached the data to be accessed; accordingly, in order to meet the exclusive permission requested by the access request, the processor core that has cached the data to be accessed may be determined based on the host cache record table, and the data processing request may be sent to the processor core that has cached the data to be accessed (for example, the processor core 1 has cached the data to be accessed in the figure) to acquire the data to be accessed and evict the cache data corresponding to the processor core.
Step S422: the processor core 1 responds to the data processing request, sends the data to be accessed to the probe filter, and evicts the cache data corresponding to the data to be accessed.
Where, the data to be accessed may be sent to the probe filter as a response message, and meanwhile the response message is used for informing the probe filter that the corresponding cache data has been evicted.
Step S423: the probe filter acquires the data to be accessed sent by the processor core.
It can be understood that after the processor core sends the data to be accessed, the probe filter may acquire the corresponding data to be accessed.
Step S424: the probe filter sends the data to be accessed to the peripheral device.
After acquiring the data to be accessed, the probe filter may send the data to be accessed to the peripheral device, such that the peripheral device acquires the data to be accessed.
It can be understood that the above data access flow is used to enable the peripheral device to exclusively own the cache data of the host cache: accordingly, after step S424 is executed, the updating process of device cache information is executed, such that the device cache information indicates that the corresponding data in the memory is cached by the peripheral device as exclusive: specifically, step S150 is executed for sending the device cache information updating request to the memory controller to update the device cache information in the memory, such that the device cache information indicates that the corresponding data in the memory is cached by the peripheral device as exclusive. Accordingly, in step S160, the memory controller updates the device cache information corresponding to the data to be accessed in the memory as exclusive based on the device cache information updating request.
It is noted that after step S150 is executed, step S425 may be further executed for updating a status entry of the corresponding cache data in the host cache record table, that is, deleting the status entry of the corresponding cache data in the host cache record table, such that the host cache record indicates that the host cache does not cache the corresponding data to be accessed.
It can be seen that the data access method provided by the embodiment of the present disclosure can implement corresponding access based on the information recorded in the host cache record table.
Next, the cache status recording apparatus and the data access apparatus provided by the embodiments of the present disclosure are introduced. The cache status recording apparatus and the data access apparatus described below may be considered as functional modules that the probe filter requires to be provided with to implement the cache status recording method and the data access method provided by the embodiments of the present disclosure. The contents of the cache status recording apparatus and the data access apparatus described below may be referred to in correspondence with the contents of the method described above.
In an alternative implementation,
Alternatively, the cache status recording apparatus may further include: an updating request sending module 110 configured to: when the peripheral device exclusively caches data, send a device cache information updating request to update device cache information in the memory, such that the device cache information indicates that corresponding data in the memory is cached by the peripheral device as exclusive.
Alternatively, the identifier updating module 100 is further configured to delete a status entry corresponding to the cache data in the host cache record table when the peripheral device exclusively owns the cache data.
Alternatively, the identifier updating module 100 is further configured to update a status of the corresponding cache data in the host cache in the host cache record table when the processor core exclusively owns the cache data, such that the status of the cache data in the host cache record table indicates that the cache data is exclusively owned by the processor core.
Alternatively, the updating request sending module 110 is further configured to: when the processor core exclusively owns the cache data and the host cache record table does not have a cache status of the data to be accessed, and
In an alternative implementation,
Alternatively, in the access request, the request initiator is a peripheral device, and a device cache of the peripheral device requests to acquire a sharing permission of the data to be accessed:
Alternatively, in the access request, the request initiator is one processor core of a plurality of processor cores, and the processor core requests to acquire an exclusive permission of the data to be accessed:
Alternatively, when the cache status of the data to be accessed does not exist in the host cache record table, the processing, by the access processing module 220, the data to be accessed based on a permission that the access request to acquire and the information in the host cache record table includes:
Alternatively, in the access request, the request initiator is a peripheral device, and the peripheral device requests to acquire an exclusive permission of the data to be accessed:
Embodiments of the present disclosure also provide a storage medium having one or more executable instructions stored thereon, the one or more executable instructions are used for executing the cache status recording method provided by the embodiments of the present disclosure, or executing the data access method provided by the embodiments of the present disclosure.
It can be seen that according to the cache status recording solution and the data access solution provided by embodiments of the present disclosure, based on a peripheral sharing identifier recorded in a host cache record table, a main status that affects a data processing flow can be determined, such that the cache data status can be recorded in the peripheral device, and then a corresponding access flow can be executed based on information of the host cache record table.
Although embodiments of the present disclosure are described herein, the present disclosure is not limited to this. Any technical personnel in this field may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope limited by the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211593112.3 | Dec 2022 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/116416 | 9/1/2023 | WO |
