Claims
- 1. A method for updating an LRU array in a cache having a RAM, said LRU array having a self-timing signal for the read operation of said LRU array, in conjunction with a cache RAM read cycle, comprising the steps of:
- beginning a cache RAM read cycle;
- determining whether a hit condition exists with respect to a tag associated with said LRU array, and generating said self-timing signal if said hit condition exists;
- beginning an LRU write operation with respect to said LRU array in response to said self-timing signal and in said cache RAM read cycle, said LRU write operation including the steps of
- providing a write signal to said LRU array, and
- pre-charging said LRU array; and
- extending said LRU write operation for a time sufficient for said precharging of said LRU bit line to complete.
- 2. A method according to claim 1, wherein said step of extending said LRU write operation is performed by extending said LRU write operation beyond said cache RAM read cycle.
- 3. A method according to claim 1, wherein said LRU array has an LRU dummy cell, and wherein
- said LRU write operation is performed by additionally providing a write signal to said LRU dummy cell, so as to perform a dummy cell write operation; and
- said step of precharging said LRU array is performed based on the completion of said dummy cell write operation.
- 4. A method according to claim 3, wherein said step of extending said LRU write operation is performed by extending said LRU write operation beyond said cache RAM read cycle.
Parent Case Info
This application is a Continuation of application Ser. No. 08/136,638, filed Oct. 12, 1993 now abandoned.
US Referenced Citations (6)
Continuations (1)
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Number |
Date |
Country |
Parent |
136638 |
Oct 1993 |
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