Calculating display mode values

Abstract

Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.

Description

BACKGROUND

[0002] This invention relates to calculating display mode values.

[0003] A display streamer in a graphics processor requests display data from memory to be temporarily stored in a FIFO (first-in first-out) and continuously feeds the display data to a display engine. Any break or interruption in feeding the display data results in visual artifacts in the final output (display) on a display device, e.g., an analog cathode ray tube (CRT) monitor. Additionally, the memory is usually most efficient when providing data at a high rate while the graphics processor can usually only use data at a rate that is much lower than this high rate.

[0004] To eliminate these visual artifacts and increase efficiency, the display streamer may be programmed with a watermark value and a burst length value for each display mode supported by the graphics processor. A display mode can be, e.g., a combination including display device resolution, color depth or pixel depth, refresh rates, and system configuration. The watermark value represents a FIFO size and falls between the minimum and maximum size of the FIFO, usually expressed in quadwords (QW) that are blocks of eight bytes each.

[0005] When the amount of data in the FIFO drops below the watermark value for the current display mode, the display streamer requests more display data from memory. A display mode's burst length value falls between the minimum and maximum amounts of display data, usually expressed in QW, that the display streamer may request from memory at a time. Analytic models may be used to predict the watermark values and burst length values for each display mode. There are over one hundred display modes.

DESCRIPTION OF DRAWINGS

[0006] FIG. 1 is a block diagram of a computer system in accordance with an embodiment of the invention.

[0007] FIG. 2 is a block diagram of a display system included in the computer system of FIG. 1.

[0008] FIG. 3 is a diagram of the display system of FIG. 2.

[0009] FIG. 4 is a flowchart of calculating and programming display mode values in accordance with an embodiment of the invention.

[0010] FIG. 5 is a graph showing display mode values.

DESCRIPTION

[0011] Referring to FIG. 1, a system 10 includes a central processing unit (CPU) 12 that computes watermark values and burst length values “on the fly” as the system 10 encounters different display modes. Different display modes result from different configurations of the system 10. A configuration can be, e.g., a particular combination of multiple displays, display resolutions, color depths, refresh rates, overlay scaling conditions, video capture conditions, and/or other system configurations. The CPU 12 programs one of the watermark values as a current watermark value and one of the burst length values as a current burst length value into a graphics controller for use in processing the graphics or video data destined for display on one or more display devices 22. The graphics controller could be included in either a graphics/memory controller (GMCH) 14 or a graphics controller (Gfx) 16 hanging on an accelerated graphics port (AGP) 18. In this embodiment, assume that the graphics controller is included in the GMCH 14. The GMCH 14 uses these values in streaming video or graphics image data. This data can be lines of the image held in main memory, e.g., dynamic random access memory (DRAM) 20, to a display device 22, e.g., a computer monitor, a television, or a floating point display unit.

[0012] Also referring to FIG. 2, a software driver (not shown) and/or a hardware logic unit (not shown) included in the CPU 12 calculates the watermark values and burst length values using the formulas discussed below and programs a display streamer 30 in the GMCH 14 with a watermark value and a burst length value for the current display mode, the present display mode of the system 10. These values enable the display streamer 30 to more efficiently control how and when the data is fetched from any data source, including local memory 32 and/or main memory 36, e.g., DRAM or synchronous dynamic random access memory (SDRAM), and provided to a display mechanism such as a display engine 34, a device that provides the display device 22 with displayable data. Local memory 32 may be included in the GMCH 14, in the Gfx 16, or as a separate unit.

[0013] Any hardware system having a memory that can store data included in an isochronous data stream, i.e., real-time, non-display data streams, e.g., modems, LANs (local area networks), and other real-time systems with event deadlines, can compute watermark and burst length values “on-the-fly” using the formulas below. The hardware system can use the software driver and/or the hardware logic unit to compute the watermark and burst length values and improve the efficiency of transferring the isochronous data between the memory and a destination of the isochronous data included in the hardware system.

[0014] Also referring to FIG. 3, a display FIFO 40 located between the memory controller 31 and the display engine 34 eliminates visual artifacts and smooth out delay jitters. Delay jitters manifest as flickers or breaks on the display device 22 and smoothing them out produces more pleasing video or graphics images, ones with less visual artifacts. The display FIFO 40 holds up to a certain number of quadwords (QW) of data fetched from local memory 32 or main memory 36, ready to be processed by the display engine 34 and shown on the display device 22. If the local memory 32 is a separate unit, it can connect to the memory controller 31 and use the main memory 36.

[0015] Storing QW of data in the display FIFO 40 can help increase efficiency of the data transfer between the memory and the graphics controller. The memory can provide data at one rate while the graphics controller can use data at another, slower rate by storing data the graphics controller is not ready to use in the FIFO 40.

[0016] The maximum size of the display FIFO 40 depends on the worst case delay (maximum latency, Lmax), the FIFO fill rate, and the FIFO drain rate. The arbitration policy in the memory controller 14 determines Lmax. For example, the display engine 34 may be granted access to local memory 32 more frequently than other isochronous clients such as a video capture engine 42 or an overlay scaling engine 44 and more frequently than non-isochronous clients such as a two-dimensional engine 46. The value of Lmax represents the maximum amount of time in clock cycles that the display engine 34 may have to wait before winning another arbitration event and gaining access to local memory 32 to obtain data to occupy the display FIFO 40. The speed of the SDRAM 36 determines the FIFO fill rate (φ), expressed in QW per local memory clock cycle. The FIFO drain rate (δ), expressed in QW per clock cycle, is determined by the rate at which data is consumed by the display engine 34. The display resolution and the refresh rate contribute to δ as shown below.

[0017] The display streamer 30 uses the watermark value (λ) and the burst length value (β) calculated by the driver and/or the hardware logic unit in the CPU 12 and programmed into a register included in the display streamer 30 in continuously monitoring the level of data in the display FIFO 40 and ensuring that the display engine 34 receives a continuous flow of data. If the FIFO level falls below λ, the display streamer 30 issues a request in a burst action to local memory 32 or main memory 20, 36 for an amount of data equal to β to occupy the display FIFO 40.

[0018] The driver and/or hardware logic unit in the CPU 12 chooses λ as a value between a minimum watermark value (λmin) and a maximum watermark value (λmax). λmin is the value which avoids FIFO underflows and delay jitter. λmin is given by:

λmin=Lmax×δ

[0019] Because this formula likely returns λmin as a floating point number and because computer systems operate with integers, the driver and/or hardware logic unit computes λmin with a ceiling subroutine as the smallest integer value greater than the floating point value of λmin. A λmin at this integer value helps the display FIFO 40 avoid underflows because λmin is greater than the FIFO drain during Lmax cycles of waiting.

[0020] The amount of data in QW (β) that the display streamer 30 requests in response to detecting a data level below λ in the display FIFO 40 falls between a minimum burst length value (βmin) and a maximum burst length value (βmax) βmin is given by: 1${\beta }_{\min }={\lambda }_{\min }\times \left(\frac{\phi }{\phi -\delta }\right)$

[0021] As with λmin, the driver and/or hardware logic unit computes βmin with a ceiling subroutine as the smallest integer value greater than the floating point value of βmin. This integer βmin value ensures that the display streamer 30 requests enough QW to guarantee that the level of the display FIFO 40 meets or exceeds λmin at the end of the burst.

[0022] To ensure that the display FIFO 40 does not overflow, the display streamer 30 should not request more QW than a maximum burst length value (βmax) in a given burst. βmax is given by: 2${\beta }_{\max }=\left(\Phi -{\lambda }_{\min }\right)\times \left(\frac{\phi }{\phi -\delta }\right),$

[0023] where Φ equals the size of the display FIFO 40 in QW. Since this βmax formula likely returns a floating point value, the driver and/or hardware logic unit uses a floor subroutine to calculate an integer βmax value that is the largest integer value less than the floating point value of βmax.

[0024] Also to help prevent overflow, the maximum watermark level (λmax) indicates the maximum amount of data that the display FIFO 40 may contain when the display streamer 30 begins a burst without overflowing the display FIFO 40 with the requested data. λmax is given by:

λmax=Φ−(Lmax×δ)

[0025] As with βmax, the driver and/or hardware logic unit uses a floor subroutine to calculate an integer value of λmax that is the largest integer value less than the floating point value of λmax.

[0026] Also referring to FIG. 4, the driver and/or hardware logic unit in the CPU 12 uses a process 50 to calculate the watermark value and the burst length value for a current display mode. The process 50 begins (52) by determining (54) any constraints of the system hardware under the current display mode from the graphics/memory controller 14, graphics controller 12, and/or the display device 22. Such constraints may include memory speed, multiple displays, overlay scaling functions, and/or video capture functions. For example, in one current display mode, the display FIFO 40 size is 48 QW, local memory 32 is running at 133 MHz and the worst case latency (Lmax) for the display streamer 30 is forty cycles. The driver and/or hardware logic unit also identifies (56) parameters of the display device 22 such as supportable resolutions, color depth, and refresh rates. In the current display mode, the display device 22 has a 1280×1024 resolution running at a 100 Hz refresh rate in 16 bpp (bits per pixel) mode. Based on these constraints and parameters, the driver and/or hardware logic unit can calculate (58) φ, the FIFO fill rate. Assume that φ equals one in the current display mode. The driver and/or hardware logic unit may determine (54) the hardware constraints and identify (56) the display device's parameters in any order.

[0027] The driver and/or hardware logic unit then determines (60) if Φ, the size of the display FIFO 40, is large enough for a specified drain rate δ and Lmax using the comparative formula:

Φ>2×Lmax×δ,

[0028] where δ equals approximately 0.357 and is given by: 3$\delta =\left(\mathrm{display}\mathrm{clock}\mathrm{frequency}\right)\times \left(\frac{\mathrm{bytes}\mathrm{per}\mathrm{pixel}}{\mathrm{bytes}\mathrm{per}\mathrm{QW}\times \mathrm{memory}\mathrm{speed}}\right)$

[0029] The display clock frequency (DCF) depends on the current display mode and can be expressed in an empirical formula as:

DCF =(horizontal resolution)×(vertical resolution)×(refresh rate)×1.45,

[0030] where 1.45 is a multiplying factor. Other methods may be used to calculate the DCF, e.g., a table-based method or a Video Electronics Standards Association generalized timing formula (VESA GTF). If Φ is not large enough, then the display FIFO 40 is too small to handle the requirements of the current display mode and the process 50 fails (62). If Φ is large enough, then the driver and/or hardware logic unit may proceed to calculate (64) the watermark value and the burst length value for the current display mode.

[0031] The driver and/or hardware logic unit calculates

[0032] integer values for λmin, λmax, βmin, and βmax as described above. In the current display mode, they respectively equal fifteen, thirty-three, twenty-four, and fifty-one. The driver and/or hardware logic unit compares (66) βmin and βmax to see if the system 10 can accommodate the current display mode. If βmax is less than βmin, then the process fails (62), and the current display mode is unsupportable. Otherwise, the driver and/or hardware logic unit compares (68) λmin and λmax. The driver and/or hardware logic unit may compare (66, 68) either burst length values or watermark values first. If λmax is greater than λmin, then the process 50 fails (62). Otherwise, the driver and/or hardware logic unit chooses (70) a watermark value λ between λmin and λmax and a burst length value β between βmin and βmax.

[0033] Also referring to FIG. 5, the driver and/or hardware logic unit chooses (70) λ and β for the current display mode from within a region 80 defined by λmin, λmax, βmin, and βmax. All of the points within the region 80 are permissible (supportable by the system 10) λ and β pairs. The driver and/or hardware logic unit preferably chooses (70) λ and β from a point in the lower left corner of the region 80. Specifically, λ is chosen (70) as the integer value of λmin and β is chosen (70) as: 4$\beta =\mathrm{ceil}\left(\frac{{\beta }_{\min }}{8}\right)\times 8,$

[0034] where “ceil” indicates the ceiling subroutine explained above. This equation forces β to meet or exceed βmin and be a multiple of eight so that the display streamer 30 can request an integer number of QW. In other embodiments, the “eights” in the above equation may equal any number, including one. Note that the region 80 shrinks for higher resolutions and refresh rates. The region 80 may not contain any permissible points indicating an unsupportable display mode. The driver and/or hardware logic unit programs (72) the chosen λ and β values into the display streamer 30 and the process 50 ends (74).

[0035] Other embodiments are within the scope of the following claims.

Claims

1. A method of determining buffer management information for a data processing system comprising: determining a latency parameter based on a first system configuration of the data processing system, the latency parameter representing a latency time amount between a display data request and delivery of display data to a display buffer; determining a buffer drain rate based on a first display mode of the data processing system; and calculating one or more buffer management parameters based on at least the latency parameter and the buffer drain rate.

2. The method of claim 1, further comprising: determining a buffer fill rate based on a buffer configuration; and calculating at least one of the one or more buffer management parameters based on the buffer fill rate.

3. The method of claim 1, further comprising: calculating at least one of the one or more buffer management parameters based on a buffer size.

4. The method of claim 1, wherein the one or more buffer management parameters comprise a watermark level.

5. The method of claim 4, wherein the watermark level comprises a lower bound of a desired watermark level range.

6. The method of claim 4, wherein the watermark level comprises an upper bound of a desired watermark level range.

7. The method of claim 1, wherein the one or more buffer management parameters comprise a burst length.

8. The method of claim 7, wherein the burst length comprises a lower bound of a desired burst length range.

9. The method of claim 7, wherein the burst length comprises an upper bound of a desired burst length range.

10. The method of claim 1, further comprising: detecting a change from the first display mode to a second display mode; and calculating at least one of the one or more buffer management parameters based on the second display mode.

11. The method of claim 1, further comprising: detecting a change from the first system configuration to a second system configuration; and calculating at least one of the one or more buffer management parameters based on the second system configuration.

12. The method of claim 1, wherein the latency parameter represents a maximum expected latency time amount for the first system configuration of the data processing system.

13. The method of claim 1, wherein the first display mode is characterized by at least one of a first refresh rate, a first display resolution, and a first color depth.

14. The method of claim 1, wherein the first system configuration is characterized at least by a buffer memory type.

15. An apparatus comprising: a display part which directs movement of display data, the display part including a buffer to store display data to be displayed on a display screen; and a data computing system configured to calculate one or more buffer management parameters based on a latency parameter based on a first system configuration and a buffer drain rate based on a first display mode; wherein the latency parameter represents a latency time amount between a display data request and delivery of display data to the buffer; and wherein the buffer drain rate represents a rate at which the display data is read from the buffer.

16. The apparatus of claim 15, wherein the data computing system is further configured to calculate at least one of the one or more buffer management parameters based on a buffer fill rate, the buffer fill rate based on a configuration of the buffer.

17. The apparatus of claim 15, wherein the data computing system is further configured to calculate at least one of the one or more buffer management parameters based on a buffer size.

18. The apparatus of claim 15, wherein the one or more buffer management parameters comprise a watermark level.

19. The apparatus of claim 18, wherein the watermark level comprises a lower bound of a desired watermark level range.

20. The apparatus of claim 18, wherein the watermark level comprises an upper bound of a desired watermark level range.

21. The apparatus of claim 15, wherein the one or more buffer management parameters comprise a burst length.

22. The apparatus of claim 21, wherein the burst length comprises a lower bound of a desired burst length range.

23. The apparatus of claim 21, wherein the burst length comprises an upper bound of a desired burst length range.

24. The apparatus of claim 15, wherein the data computing system is further configured to detect a change from a first display mode to a second display mode, and in response to the detecting is further configured to calculate at least one of the one or more buffer management parameters based on the second display mode.

25. The apparatus of claim 15, wherein the data computing system is further configured to detect a change from a first system configuration to a second system configuration, and in response to the detecting is further configured to calculate at least one of the one or more buffer management parameters based on the second system configuration.

26. The apparatus of claim 15, wherein the latency parameter represents a maximum expected latency time amount for the first system configuration.

27. The apparatus of claim 15, wherein the first display mode is characterized by at least one of a first refresh rate, a first display resolution, and a first color depth.

28. The apparatus of claim 15, wherein the first system configuration is characterized at least by a first buffer memory type.

29. An article comprising a storage medium which stores computer-executable instructions, the instructions causing a computer to perform operations comprising: determining a latency parameter based on a first system configuration of the data processing system, the latency parameter representing a latency time amount between a display data request and delivery of display data to a display buffer; determining a buffer drain rate based on a first display mode; and calculating one or more buffer management parameters based on at least the latency parameter and the buffer drain rate.

30. The article of claim 29, the operations further comprising: determining a buffer fill rate based on a buffer configuration; and calculating at least one of the one or more buffer management parameters based on the buffer fill rate.

31. The article of claim 29, the operations further comprising: calculating at least one of the one or more buffer management parameters based on a buffer size.

32. The article of claim 29, wherein the one or more buffer management parameters comprise a watermark level.

33. The article of claim 32, wherein the watermark level comprises a lower bound of a desired watermark level range.

34. The article of claim 32, wherein the watermark level comprises an upper bound of a desired watermark level range.

35. The article of claim 29, wherein the one or more buffer management parameters comprise a burst length.

36. The article of claim 35, wherein the burst length comprises a lower bound of a desired burst length range.

37. The article of claim 35, wherein the burst length comprises an upper bound of a desired burst length range.

38. The article of claim 29, the operations further comprising: detecting a change from the first display mode to a second display mode; and calculating at least one of the one or more buffer management parameters based on the second display mode.

39. The article of claim 29, the operations further comprising: detecting a change from the first system configuration to a second system configuration; and calculating at least one of the one or more buffer management parameters based on the second system configuration.

40. The article of claim 29, wherein the latency parameter represents a maximum expected latency time amount for the first system configuration of the data processing system.

41. The article of claim 29, wherein the first display mode is characterized by at least one of a first refresh rate, a first display resolution, and a first color depth.

42. The article of claim 29, wherein the first system configuration is characterized at least by a buffer memory type.

43. A system, comprising: a display; a display part which directs movement of display data to the display, the display part including a buffer to store display data to be displayed on the display; and a data processor configured to calculate one or more buffer management parameters based on a latency parameter based on a first system configuration and a buffer drain rate based on a first display mode; wherein the latency parameter represents a latency time amount between a display data request and delivery of display data to the buffer; and wherein the buffer drain rate represents a rate at which the display data is read from the buffer.

44. The system of claim 43, wherein the data processor is further configured to calculate at least one of the one or more buffer management parameters based on a buffer fill rate, the buffer fill rate based on a configuration of the buffer.

45. The system of claim 43, wherein the data processor is further configured to calculate at least one of the one or more buffer management parameters based on a buffer size.

46. The system of claim 43, wherein the one or more buffer management parameters comprise a watermark level.

47. The system of claim 46, wherein the watermark level comprises a lower bound of a desired watermark level range.

48. The system of claim 46, wherein the watermark level comprises an upper bound of a desired watermark level range.

49. The system of claim 43, wherein the one or more buffer management parameters comprise a burst length.

50. The system of claim 49, wherein the burst length comprises a lower bound of a desired burst length range.

51. The apparatus of claim 49, wherein the burst length comprises an upper bound of a desired burst length range.

52. The system of claim 43, wherein the data processor is further configured to detect a change from a first display mode to a second display mode, and in response to the detecting is further configured to calculate at least one of the one or more buffer management parameters based on the second display mode.

53. The system of claim 43, wherein the data processor is further configured to detect a change from a first system configuration to a second system configuration, and in response to the detecting is further configured to calculate at least one of the one or more buffer management parameters based on the second system configuration.

54. The system of claim 43, wherein the latency parameter represents a maximum expected latency time amount for the first system configuration.

55. The system of claim 43, wherein the first display mode is characterized by at least one of a first refresh rate, a first display resolution, and a first color depth.

56. The apparatus of claim 43, wherein the first system configuration is characterized at least by a first buffer memory type.