In a computer network having a plurality of network segments, a clock distribution system is required for synchronising one or more clocks in the communication system of each segment. The architecture of a clock distribution system may for example be based on NTP (Network Time Protocol) or PTP (Precision Time Protocol) including IEEE1588 V1, IEEE1588 V2 and IEEE802.1AS (incorporated herein by reference). The one or more clocks may for example be an ordinary clock, a boundary clock or a transparent clock. For a communication system with a plurality of clocks, the plurality of clocks may include a source of synchronisation reference—a master device—and a destination for the synchronisation reference—a slave device, and the master and slave devices are generally connected via an uplink connection for transmissions from the slave device to the master device, and a downlink connection for transmission from the master device to the slave device, where the uplink and downlink connections may be optical waveguides such as optical fibres.
According to an example, a slave device calculates a time offset based on a downlink delay time and an uplink delay time between a master device and the slave device so as to synchronised with reference to the master device. Since both a downlink delay time and an uplink delay time are separately obtained, instead of assuming that the two delay times are the same, the contribution to the time offset from the delays in the downlink path and the uplink path between the slave device and the master device may be more accurately obtained.
In the example, the slave device obtains the downlink delay time based on a first transmission time and a first reception time by sending a first test signal via a downlink optical waveguide to the master device and recording the first transmission time, and receiving the first test signal looped back by the master device via the downlink optical waveguide and recording the first reception time. The slave device obtains the uplink delay time based on a second transmission time and a second reception time by sending a second test signal via an uplink optical waveguide to the master device and recording the second transmission time, and receiving the second test signal looped back by the master device via the uplink optical waveguide and recording the second reception time. Since the test signals are looped back by the master device, it is possible to minimise any processing time at the master device, and obtain only the time delay caused by the transit over the uplink and downlink connections. Moreover, as both the transmission time and the reception time of a test signal may be collected at the slave device, which is the side to be synchronised, the efficiency of time measurement is improved.
An example of a communication system is schematically shown in
At block 201, the slave device 120 obtains a downlink delay time that is a transit time for transmission to travel between the slave device 120 and the master device 110 via the downlink connection.
In the example, the slave device 120 sends a downlink delay test message (first test signal) via the downlink optical fibre to the master device 110, and records the time at which the downlink delay test message was transmitted as a first transmission time T1down. Upon receiving the downlink delay test message, the master device 110 loops the downlink delay test message back to the slave device 120 via the downlink optical fibre. For example, the master device 110 may perform the loopback using a loopback module 115 such as a commercially available loopback device, a 1:2 optical beam splitter, or any other devices suitable for loopback. The slave device 120 records the time at which the looped back downlink delay test message is received as a first reception time T2down. Using the first transmission time and the first reception time, the slave device 120 calculates the downlink delay time.
At block 202, the slave device 120 obtains an uplink delay time that is a transit time for transmission to travel between the slave device 120 and the master device 110 via the uplink connection.
In the example, the slave device 120 sends an uplink delay test message (second test signal) via the uplink optical fibre to the master device 110, and records the time at which the uplink delay test message was transmitted as a second transmission time T1up. Upon receiving the uplink delay test message, the master device 110 loops the uplink delay test message back to the slave device 120 via the uplink optical fibre using a suitable loopback module 115. The slave device 120 records the time at which the looped back uplink delay test message is received as a second reception time T2up. Using the second transmission time and the second reception time, the slave device 120 calculates the uplink delay time.
At block 203, the slave device 120 calculates a time offset between the master device 110 and the slave device 120 based on the obtained downlink delay time and uplink delay time.
In the example, separately obtained downlink delay time and uplink delay time are used for determining the time offset between the master device and the slave device. In this case, it is possible to separately determine the transit time which a downlink signal would take to travel from the master device to the slave device via the downlink connection, and the transit time which an uplink signal would take to travel from the slave device to the master device via the uplink connection. Compared to the case in which both downlink and uplink are assumed to have the same delay, the present example is able to obtain a more accurate time offset.
In an example, the downlink delay time may be obtained by calculating a downlink path delay PathDelaydown=(T2down−T1down)/2 using the first transmission time T1down and the first reception time T2down. Since the time difference (T2down−T1down) is a round-trip time, it is divided by 2 to obtain the path delay for a single trip. In another example, the downlink delay may be obtained by repeating the measurement of T1down and T2down a plurality of times to calculate the respective PathDelaydown, and averaging the plurality of PathDelaydown. In the case where multiple values of PathDelaydown are obtained, it may be desirable to eliminate any values of PathDelaydown that appears abnormal, for example unusually large or small values, before averaging the plurality of PathDelaydown, in order to obtain a more accurate and reliable downlink delay time.
In an example, the uplink delay time may be obtained by calculating an uplink path delay PathDelayup=(T2up−T1up)/2 using the second transmission time T1up and the second reception time T2up. Again, since the time difference (T2up−T1up) is a round-trip time, it is divided by 2 to obtain the path delay for a single trip. In another example, the uplink delay may be obtained by repeating the measurement of T1up and T2up a plurality of times and calculating the respective PathDelayup, and averaging the plurality of PathDelayup. In the case where multiple values of PathDelayup are obtained, it may be desirable to eliminate any values of PathDelayup that appears abnormal before averaging the plurality of PathDelayup, in order to obtain a more accurate and reliable uplink delay time.
In an example, the clock synchronisation between the master device and the slave device may be performed according to a IEEE1588 protocol or any other suitable clock synchronisation protocols. In particular, the offset between the master device and the slave device may be calculated using the expression,
where Δsm is an absolute delay between the slave device and the master device.
The absolute delay Δsm represents systematic delays between the time at which the master device sends a signal until the time at which the slave device receives the signal, which may include processes that take place within the master device from the time the signal is generated to the time the signal is timestamped by the master device, and from the time the signal is timestamped to the time at which the signal arrives at the physical interface of the master device.
On the other hand, the downlink path delay PathDelaydown and the uplink path delay PathDelayup determined according to the example use test signals directly looped back by the master device without processing. Thus, the downlink path delay PathDelaydown and the uplink path delay PathDelayup represent delays caused only by network connections that respectively form the downlink connection and the uplink connection. By determining the offset in time between the master device and itself, the slave device may then adjust its clock accordingly to be in synchronisation with the master device. In the example, PathDelaydown and PathDelayup may be determined as described above as a single value or an average of multiple values. The quantity (PathDelaydown|PathDelayup)/2 represents the asymmetry between the delay in the downlink connection and the delay in the uplink connection. Thus, in an example, the slave device may calculate a time offset between the master device and the slave device using the delay asymmetry DelayAsymmetry=(PathDelaydown−PathDelayup)/2.
An example of a communication system that performs clock synchronisation using the method described above is shown in
In
In the example, referring to
The loopback module 315 of the master device 310 receives the downlink delay test message via the downlink optical fibre and loops the downlink delay test message back down the downlink optical fibre.
The optical module 325 receives the downlink delay test message looped back by the master device 310 via the downlink optical fibre, and the timestamp module 323 records the time at which the downlink delay test message is received as a first reception time T2down. The timestamp module 323 then calculates a downlink delay time based on the first transmission time T1down and the first reception time T2down.
In an example, the timestamp module may be configured to calculate the downlink delay time by calculating a downlink path delay PathDelaydown=(T2down−T1down)/2 using the first transmission time T1down and the first reception time T2down.
Referring now to
The synchronization module 311 of the slave device 320 then generates an uplink delay test message (second test signal) and forwards the uplink delay test message to the optical module 325 via the MAC chip 322. The optical module 325 sends the uplink delay test message down the uplink optical fibre, and the timestamp module 323 records the time at which the uplink delay test message is sent as a second transmission time T1up.
The loopback module 315′ of the master device 310 receives the uplink delay test message via the uplink optical fibre and loops the uplink delay test message back down the uplink optical fibre.
The optical module 325 receives the uplink delay test message looped back by the master device 310 via the uplink optical fibre, and the timestamp module 323 records the time at which the uplink delay test message is received as a second reception time T2up. The timestamp module 323 then calculates an uplink delay time based on the second transmission time T1up and the second reception time T2up.
The timestamp module 323 calculates a time offset between the master device and the slave device based on the downlink delay time and the uplink delay time.
In an example, the timestamp module 323 may be configured to calculate the uplink delay time by calculating an uplink path delay PathDelayup=(T2up−T1up)/2 using the second transmission time T1up and the second reception time T2up.
In an example, the optical module 325 may be any suitable optical module including a single strand bidirectional optical transceiver, the loopback module 315 and 315′ may be any suitable loopback device including a beam splitter.
According to the examples above, since both a downlink delay time and an uplink delay time are separately obtained, the time offset between the slave device and the master device may be more accurately determined.
According to the examples above, since the test signals are looped back by the master device, no processing is required at the master device side and the master device is not required to generate and transmit a separate test signal, thus it is possible to separate network transit delays from systematic delays. Moreover, both the transmission time and the reception time of a test signal may be collected at the slave device that is the side to be synchronised, thus it is possible to improve efficiency.
In the examples above, the clock synchronisation method is applied to IEEE1588 protocol. However, the clock synchronisation method may be applied to various versions of IEEE1588 and other time synchronisation protocols such as NTP.
Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted.
The above examples can be implemented by hardware, software, firmware, or a combination thereof. For example, the various methods and functional modules described herein may be implemented by a processor (the term processor is to be interpreted broadly to include a CPU, processing unit, ASIC, logic unit, or programmable gate array etc.). The methods and functional modules may all be performed by a single processor or divided amongst several processors. The methods and functional modules may be implemented as machine readable instructions executable by one or more processors, hardware logic circuitry of the one or more processors, or a combination thereof. Further, the teachings herein may be implemented in the form of a software product, the computer software product being stored in a storage medium and comprising a plurality of instructions for making a computer device (e.g. a personal computer, a server or a network device such as a router, switch, access point etc.) implement the method recited in the examples of the present disclosure.
It should be understood that embodiments of the clock synchronisation method for a communication system described above are implementation examples only, and do not limit the scope of the invention. Numerous other changes, substitutions, variations, alternations and modifications may be ascertained by those skilled in the art, and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations and modifications as falling within the spirit and scope of the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
201211084146.X | Mar 2012 | CN | national |
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/CN2013/072354 | 3/8/2013 | WO | 00 |