Patent Application
20140001978
1. Field of the Invention
The present invention is related to a calibration apparatus and method thereof.
2. Description of the Prior Art
Current balance is an important specification for an LED (Light Emitting Diode) driving circuit driving chains of LEDs. In conventional specification, the uniformity for the chains of LEDs is required to be within 1%. However, due to the variation in process parameters during manufacturing, the electronic components of the LED driving circuit may not be able to meet the specification of current balance.
However, error amplifiers OPA1 and OPA2 of multi-channel LED driving circuit 100 may not have ideal characteristics. Due to process variations, error amplifiers OPA1 and OPA2 may exhibit unmatched offset voltages, the difference between which is likely to hinder multi-channel LED driving circuit 100 from meeting the specification of current balance.
The present invention provides a calibration method for adjusting an offset voltage of a unit under calibration. The unit under calibration, having a first input terminal, a second input terminal and an output terminal, is configured to operate in a calibration mode or a normal mode. The calibration method includes operating the unit under calibration in the calibration mode, providing a programmable voltage to the first input terminal, providing a constant voltage to the second input terminal, adjusting the programmable voltage monotonously when an output status of the output terminal remains unchanged, latching the programmable voltage when the output status toggles, and operating the unit under calibration in the normal mode after the output status toggles.
The present invention further provides a calibration apparatus for compensating an offset voltage of a comparator which includes a first input terminal, a second input terminal and an output terminal. The calibration apparatus includes a counter configured to adjust a digital signal monotonously, a programmable voltage generating unit configured to generate a programmable voltage on the first terminal according to a first input voltage and the digital signal, and a latch circuit configured to generate a latched digital signal by latching the digital signal when an output status of the output terminal changes, thereby preventing the programmable voltage from being interfered by the counter. A second input voltage is supplied to the second input terminal and the difference between the first and second input voltages is a constant value.
The present invention further provides a multi-channel driving circuit which provides current balancing. The multi-channel driving circuit includes a plurality of current driving circuits each configured to control a corresponding channel current according to a channel current control voltage. Each current driving circuit includes a comparator having a first input terminal, a second input terminal and an output terminal for controlling the corresponding channel current; a latch circuit configured to provide a latched digital signal; and a compensation voltage generator configured to generate a compensation voltage according to the latched digital signal. A sum of the compensation voltage and a first input voltage is supplied to one input terminal among the first and second input terminals. A second input voltage is supplied to the other input terminal among the first and second input terminals. One input voltage among the first and second input voltages corresponds to the channel current. The other input voltage among the first and second input voltages corresponds to the channel current control voltage.
The present invention further provides a current balancing method for driving multiple channels. The current balancing method includes adjusting a digital signal monotonously and, for each corresponding channel, adjusting a compensation voltage according to the digital signal, providing a sum of the compensation voltage and a first input voltage to a first input terminal of a comparator, providing a second input voltage to a second input terminal of the comparator, generating a latched digital signal by latching the digital signal when an output status of an output terminal of the comparator changes, and controlling the comparator according to the latched digital signal, a channel current control voltage and a corresponding feedback voltage for driving the corresponding channel. A difference between the first and second input voltages is a constant value, and the corresponding feedback voltage is associated with a current flowing through the corresponding channel.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
In the normal mode when switch S1 is turned on (short-circuited), calibration circuit 211 may provide level shift to reference voltage VREF, feedback voltage V3 (the voltage signal fed from resistor R3), or both. Calibration circuit 211 converts reference voltage VREF and feedback voltage V3 into two input voltages Vi1 and Vi2 based on which error amplifier OPA3 may control the control terminal of transistor switch M5, thereby regulating the current flowing through resistor R3. Therefore, calibration circuit 211 and error amplifier OPA3 together function as equivalent error amplifier OPAX, to which reference voltage VREF and feedback voltage V3 are supplied as the two input signals. Reference voltage VREF may be viewed as a channel current control voltage. The amount of constant level shift provided by calibration circuit 211 is determined in the calibration mode.
In the calibration mode, switch S1 is turned off (open-circuited). In one embodiment, calibration circuit 211 provides two input voltages Vi1 and Vi2 to error amplifier OPA3 by commonly shifting reference voltage VREF. In one embodiment, voltage shift Vshift1, the difference between reference voltage VREF and input voltages Vi1 varies with the output of counter 203, while voltage shift Vshift2, the difference between reference voltage VREF and input voltages Vi2, is constant. After entering the calibration mode, output of counter 204 increases or decreases monotonously, and voltage shift Vshift1 provided by calibration circuit 211 increases or decreases with the output of counter 203 accordingly. After the offset voltage of error amplifier OPAX reaches a predetermined value, output VTR1 of error amplifier OPA3 toggles. After then, calibration circuit 211 is configured to latch voltage shift Vshift1 so as to prevent interference associated with the output of counter 203. As counter 203 continues to vary, the voltage shifts of other calibration circuits (such as that of calibration circuit 222) may be adjusted until the voltage shift provided by each calibration circuit has been latched. Latched voltage shift Vshift1 and constant voltage shift Vshift2 may thus be used in the normal mode. Under such circumstance, the voltage shift of the equivalent error amplifier in each current driving circuit may be maintained within a range defined by the same predetermined value, which allows multi-channel LED driving circuit 200 to meet the specification of current balance.
In the calibration mode when switch S1 disconnects non-ideal error amplifier OPA3 from X3, reference voltage VREF is supplied to the control terminal of transistor M8 via switch S9, and feedback voltage V3 (the voltage signal fed from resistor R3) is isolated from the control terminal of transistor M8.
Transistor M8 and adder 305 are configured to shift reference voltage VREF, thereby generating corresponding input voltage Vi2 (on second input terminal In2 of error amplifier OPA3). Voltage shift Vshift2 may be obtained as follows:
Vshift2=Vth8+If*RR6 (1)
In equation (1), Vth8 represents the threshold voltage of transistor M8, If the current flowing through resistor R6, and RR6 the resistance of resistor R6. In this embodiment, voltage shift Vshift2 has a constant value since Vth8, M8 and If are all constants.
Digital-to-analog converter (DAC) 31 is configured to supply analog signal current I (LD)) to resistor R5 by selecting one current source or a combination of current sources from current sources I1-I5 according to digital signal LD. Similar to the operation of transistor M8 and adder 305, voltage shift Vshift2 between input voltage Vi1 (on first input terminal IN1 of error amplifier OPA3) and reference voltage VREF may be obtained as follows:
Vshift1=Vth7+I(LD)*RR5 (2)
In equation (2), Vth7 represents the threshold voltage of transistor M7, and RR5 the resistance of resistor R5. In this embodiment, input voltage Vi1 is a programmable voltage since the current flowing through resistor R5 may be programmed according to digital signal LD.
Upon entering the calibration mode, latch circuit 301 does not function, and digital signals LD and SD both increase or decrease monotonously with counter 203. As digital signal LD varies, voltage shift Vshift1 and input voltage Vi1 also change accordingly. Once the difference between input voltages Vi1 and Vi2 exceeds a specific value, error amplifier OPA3 changes its output signal VTR1, which in turn triggers latch circuit 301. When latch circuit 301 is functioning, digital signal LD is latched at a constant value and no longer varies with digital signal SD. Therefore, digital signal LD may be viewed as a latched digital signal.
In the normal mode, digital signal LD remained latched and is not influenced by output signal VTR1. Switch S1 shorts output Out1 to X3, and feedback voltage V3 (the voltage signal fed from resistor R3) is supplied to the control terminal of transistor M8 via switch S9.
In
A calibration method using calibration circuit 211 is provided so that those skilled the art may practice the present invention from the disclosure.
In step 403, input voltage Vi1 supplied to first terminal In1 is (VREF+Vshift1), whose value, (1.3+LD*0.001)V, may be programmed by digital signal LD; input voltage Vi2 supplied to second terminal In2 is (VREF+Vshift2), which has a constant value of 1.35V. Since the initial value of counter 203 is 0, currently input voltage Vi1 is 1.3V and the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA1 is −0.02V(=1.3V+0.03V−1.35V), thereby generating logic 0 as output signal VTR1.
In step 404 when counter 203 is increased monotonously by 1, digital signals SD and LD become 1, input voltage Vi1 increases by 0.001V and becomes 1.301V, the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA1 becomes −0.019V, and output signal VTR1 remains at logic 0.
In step 405, it is determined whether the status of the output terminal changes. If output signal VTR1 remains at logic 0, the calibration method goes back to step 404 after step 405 for increasing counter 203 further by 1. Therefore, the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA1 increases by 0.001V after each time step 404 is executed. After looping back to step 404 subsequent to step 405 several times, digital signal SD may be increased to 21, and the voltage difference between the positive and negative input terminals of ideal error amplifier IOPA1 may reach 0.001V. As a result, output signal VTR1 switches to logic 1. Since the status of the output terminal has been changed, step 406 is executed after step 405 instead of looping back to step 404.
In step 406, latch circuit 301 latches the current value of digital signal LD(=21) and the states of switches SW1-SW5, thereby latching input voltage Vi1 equivalently. After that, digital signal LD in current driving circuit 201 remains constant even if counter 203 continues to increase. Under such circumstance, voltage shift Vshift1 of current driving circuit 201 is fixed to 0.821V(=0.8+21*0.001), voltage shift Vshift2 is still 0.85V, and the voltage difference between the two input terminals of equivalent error amplifier OPAX is about 0.001V(=Vshift1+Vos1−Vshift2=0.821+0.03−0.85).
In step 407, mode control unit 204 operates switches SW1 and SW9 so that the unit under calibration OPA3 may return to the same state as those of current driving circuits 15 and 16 in
The calibration method ends in step 408. When operating a current driving circuit according to the flowchart in
In the embodiment illustrated in
In the embodiment illustrated in
In the embodiment illustrated in
Normally, a driving circuit is able to execute a soft-start procedure. When multi-channel LED driving circuit 200 in
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 099111357 | Apr 2010 | TW | national |
This application is a division of U.S. application Ser. No. 12/969,572 filed on Dec. 15, 2010.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 12969572 | Dec 2010 | US |
| Child | 14019506 | US |
